arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 / {
  11         model = "Qualcomm APQ8064";
  12         compatible = "qcom,apq8064";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,krait";
  21                         enable-method = "qcom,kpss-acc-v1";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                         cpu-idle-states = <&CPU_SPC>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu@2 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <2>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc2>;
  48                         qcom,saw = <&saw2>;
  49                         cpu-idle-states = <&CPU_SPC>;
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "qcom,krait";
  54                         enable-method = "qcom,kpss-acc-v1";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                         next-level-cache = <&L2>;
  58                         qcom,acc = <&acc3>;
  59                         qcom,saw = <&saw3>;
  60                         cpu-idle-states = <&CPU_SPC>;
  61                 };
  62
  63                 L2: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <2>;
  66                 };
  67
  68                 idle-states {
  69                         CPU_SPC: spc {
  70                                 compatible = "qcom,idle-state-spc",
  71                                                 "arm,idle-state";
  72                                 entry-latency-us = <400>;
  73                                 exit-latency-us = <900>;
  74                                 min-residency-us = <3000>;
  75                         };
  76                 };
  77         };
  78
  79         cpu-pmu {
  80                 compatible = "qcom,krait-pmu";
  81                 interrupts = <1 10 0x304>;
  82         };
  83
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 tlmm_pinmux: pinctrl@800000 {
  91                         compatible = "qcom,apq8064-pinctrl";
  92                         reg = <0x800000 0x4000>;
  93
  94                         gpio-controller;
  95                         #gpio-cells = <2>;
  96                         interrupt-controller;
  97                         #interrupt-cells = <2>;
  98                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  99
 100                         pinctrl-names = "default";
 101                         pinctrl-0 = <&ps_hold>;
 102
 103                         sdc4_gpios: sdc4-gpios {
 104                                 pios {
 105                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 106                                         function = "sdc4";
 107                                 };
 108                         };
 109
 110                         ps_hold: ps_hold {
 111                                 mux {
 112                                         pins = "gpio78";
 113                                         function = "ps_hold";
 114                                 };
 115                         };
 116
 117                         i2c1_pins: i2c1 {
 118                                 mux {
 119                                         pins = "gpio20", "gpio21";
 120                                         function = "gsbi1";
 121                                 };
 122                         };
 123
 124                         i2c3_pins: i2c3 {
 125                                 mux {
 126                                         pins = "gpio8", "gpio9";
 127                                         function = "gsbi3";
 128                                 };
 129                         };
 130
 131                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 132                                 mux {
 133                                         pins = "gpio14", "gpio15";
 134                                         function = "gsbi6";
 135                                 };
 136                         };
 137
 138                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 139                                 mux {
 140                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 141                                         function = "gsbi6";
 142                                 };
 143                         };
 144
 145                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 146                                 mux {
 147                                         pins = "gpio82", "gpio83";
 148                                         function = "gsbi7";
 149                                 };
 150                         };
 151
 152                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 153                                 mux {
 154                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 155                                         function = "gsbi7";
 156                                 };
 157                         };
 158                 };
 159
 160                 intc: interrupt-controller@2000000 {
 161                         compatible = "qcom,msm-qgic2";
 162                         interrupt-controller;
 163                         #interrupt-cells = <3>;
 164                         reg = <0x02000000 0x1000>,
 165                               <0x02002000 0x1000>;
 166                 };
 167
 168                 timer@200a000 {
 169                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 170                         interrupts = <1 1 0x301>,
 171                                      <1 2 0x301>,
 172                                      <1 3 0x301>;
 173                         reg = <0x0200a000 0x100>;
 174                         clock-frequency = <27000000>,
 175                                           <32768>;
 176                         cpu-offset = <0x80000>;
 177                 };
 178
 179                 acc0: clock-controller@2088000 {
 180                         compatible = "qcom,kpss-acc-v1";
 181                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 182                 };
 183
 184                 acc1: clock-controller@2098000 {
 185                         compatible = "qcom,kpss-acc-v1";
 186                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 187                 };
 188
 189                 acc2: clock-controller@20a8000 {
 190                         compatible = "qcom,kpss-acc-v1";
 191                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 192                 };
 193
 194                 acc3: clock-controller@20b8000 {
 195                         compatible = "qcom,kpss-acc-v1";
 196                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 197                 };
 198
 199                 saw0: power-controller@2089000 {
 200                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 201                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 202                         regulator;
 203                 };
 204
 205                 saw1: power-controller@2099000 {
 206                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 207                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 208                         regulator;
 209                 };
 210
 211                 saw2: power-controller@20a9000 {
 212                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 213                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 214                         regulator;
 215                 };
 216
 217                 saw3: power-controller@20b9000 {
 218                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 219                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 220                         regulator;
 221                 };
 222
 223                 gsbi1: gsbi@12440000 {
 224                         status = "disabled";
 225                         compatible = "qcom,gsbi-v1.0.0";
 226                         cell-index = <1>;
 227                         reg = <0x12440000 0x100>;
 228                         clocks = <&gcc GSBI1_H_CLK>;
 229                         clock-names = "iface";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         ranges;
 233
 234                         syscon-tcsr = <&tcsr>;
 235
 236                         i2c1: i2c@12460000 {
 237                                 compatible = "qcom,i2c-qup-v1.1.1";
 238                                 pinctrl-0 = <&i2c1_pins>;
 239                                 pinctrl-names = "default";
 240                                 reg = <0x12460000 0x1000>;
 241                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 242                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 243                                 clock-names = "core", "iface";
 244                                 #address-cells = <1>;
 245                                 #size-cells = <0>;
 246                         };
 247                 };
 248
 249                 gsbi2: gsbi@12480000 {
 250                         status = "disabled";
 251                         compatible = "qcom,gsbi-v1.0.0";
 252                         cell-index = <2>;
 253                         reg = <0x12480000 0x100>;
 254                         clocks = <&gcc GSBI2_H_CLK>;
 255                         clock-names = "iface";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         ranges;
 259
 260                         syscon-tcsr = <&tcsr>;
 261
 262                         i2c2: i2c@124a0000 {
 263                                 compatible = "qcom,i2c-qup-v1.1.1";
 264                                 reg = <0x124a0000 0x1000>;
 265                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 266                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 267                                 clock-names = "core", "iface";
 268                                 #address-cells = <1>;
 269                                 #size-cells = <0>;
 270                         };
 271                 };
 272
 273                 gsbi3: gsbi@16200000 {
 274                         status = "disabled";
 275                         compatible = "qcom,gsbi-v1.0.0";
 276                         cell-index = <3>;
 277                         reg = <0x16200000 0x100>;
 278                         clocks = <&gcc GSBI3_H_CLK>;
 279                         clock-names = "iface";
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         ranges;
 283                         i2c3: i2c@16280000 {
 284                                 compatible = "qcom,i2c-qup-v1.1.1";
 285                                 pinctrl-0 = <&i2c3_pins>;
 286                                 pinctrl-names = "default";
 287                                 reg = <0x16280000 0x1000>;
 288                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 289                                 clocks = <&gcc GSBI3_QUP_CLK>,
 290                                          <&gcc GSBI3_H_CLK>;
 291                                 clock-names = "core", "iface";
 292                         };
 293                 };
 294
 295                 gsbi6: gsbi@16500000 {
 296                         status = "disabled";
 297                         compatible = "qcom,gsbi-v1.0.0";
 298                         cell-index = <6>;
 299                         reg = <0x16500000 0x03>;
 300                         clocks = <&gcc GSBI6_H_CLK>;
 301                         clock-names = "iface";
 302                         #address-cells = <1>;
 303                         #size-cells = <1>;
 304                         ranges;
 305
 306                         gsbi6_serial: serial@16540000 {
 307                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 308                                 reg = <0x16540000 0x100>,
 309                                       <0x16500000 0x03>;
 310                                 interrupts = <0 156 0x0>;
 311                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 312                                 clock-names = "core", "iface";
 313                                 status = "disabled";
 314                         };
 315                 };
 316
 317                 gsbi7: gsbi@16600000 {
 318                         status = "disabled";
 319                         compatible = "qcom,gsbi-v1.0.0";
 320                         cell-index = <7>;
 321                         reg = <0x16600000 0x100>;
 322                         clocks = <&gcc GSBI7_H_CLK>;
 323                         clock-names = "iface";
 324                         #address-cells = <1>;
 325                         #size-cells = <1>;
 326                         ranges;
 327                         syscon-tcsr = <&tcsr>;
 328
 329                         gsbi7_serial: serial@16640000 {
 330                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 331                                 reg = <0x16640000 0x1000>,
 332                                       <0x16600000 0x1000>;
 333                                 interrupts = <0 158 0x0>;
 334                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 335                                 clock-names = "core", "iface";
 336                                 status = "disabled";
 337                         };
 338                 };
 339
 340                 qcom,ssbi@500000 {
 341                         compatible = "qcom,ssbi";
 342                         reg = <0x00500000 0x1000>;
 343                         qcom,controller-type = "pmic-arbiter";
 344
 345                         pmicintc: pmic@0 {
 346                                 compatible = "qcom,pm8921";
 347                                 interrupt-parent = <&tlmm_pinmux>;
 348                                 interrupts = <74 8>;
 349                                 #interrupt-cells = <2>;
 350                                 interrupt-controller;
 351                                 #address-cells = <1>;
 352                                 #size-cells = <0>;
 353
 354                                 pm8921_gpio: gpio@150 {
 355
 356                                         compatible = "qcom,pm8921-gpio";
 357                                         reg = <0x150>;
 358                                         interrupts = <192 IRQ_TYPE_NONE>,
 359                                                      <193 IRQ_TYPE_NONE>,
 360                                                      <194 IRQ_TYPE_NONE>,
 361                                                      <195 IRQ_TYPE_NONE>,
 362                                                      <196 IRQ_TYPE_NONE>,
 363                                                      <197 IRQ_TYPE_NONE>,
 364                                                      <198 IRQ_TYPE_NONE>,
 365                                                      <199 IRQ_TYPE_NONE>,
 366                                                      <200 IRQ_TYPE_NONE>,
 367                                                      <201 IRQ_TYPE_NONE>,
 368                                                      <202 IRQ_TYPE_NONE>,
 369                                                      <203 IRQ_TYPE_NONE>,
 370                                                      <204 IRQ_TYPE_NONE>,
 371                                                      <205 IRQ_TYPE_NONE>,
 372                                                      <206 IRQ_TYPE_NONE>,
 373                                                      <207 IRQ_TYPE_NONE>,
 374                                                      <208 IRQ_TYPE_NONE>,
 375                                                      <209 IRQ_TYPE_NONE>,
 376                                                      <210 IRQ_TYPE_NONE>,
 377                                                      <211 IRQ_TYPE_NONE>,
 378                                                      <212 IRQ_TYPE_NONE>,
 379                                                      <213 IRQ_TYPE_NONE>,
 380                                                      <214 IRQ_TYPE_NONE>,
 381                                                      <215 IRQ_TYPE_NONE>,
 382                                                      <216 IRQ_TYPE_NONE>,
 383                                                      <217 IRQ_TYPE_NONE>,
 384                                                      <218 IRQ_TYPE_NONE>,
 385                                                      <219 IRQ_TYPE_NONE>,
 386                                                      <220 IRQ_TYPE_NONE>,
 387                                                      <221 IRQ_TYPE_NONE>,
 388                                                      <222 IRQ_TYPE_NONE>,
 389                                                      <223 IRQ_TYPE_NONE>,
 390                                                      <224 IRQ_TYPE_NONE>,
 391                                                      <225 IRQ_TYPE_NONE>,
 392                                                      <226 IRQ_TYPE_NONE>,
 393                                                      <227 IRQ_TYPE_NONE>,
 394                                                      <228 IRQ_TYPE_NONE>,
 395                                                      <229 IRQ_TYPE_NONE>,
 396                                                      <230 IRQ_TYPE_NONE>,
 397                                                      <231 IRQ_TYPE_NONE>,
 398                                                      <232 IRQ_TYPE_NONE>,
 399                                                      <233 IRQ_TYPE_NONE>,
 400                                                      <234 IRQ_TYPE_NONE>,
 401                                                      <235 IRQ_TYPE_NONE>;
 402                                         gpio-controller;
 403                                         #gpio-cells = <2>;
 404
 405                                 };
 406
 407                                 pm8921_mpps: mpps@50 {
 408                                         compatible = "qcom,pm8921-mpp";
 409                                         reg = <0x50>;
 410                                         gpio-controller;
 411                                         #gpio-cells = <2>;
 412                                         interrupts =
 413                                         <128 IRQ_TYPE_NONE>,
 414                                         <129 IRQ_TYPE_NONE>,
 415                                         <130 IRQ_TYPE_NONE>,
 416                                         <131 IRQ_TYPE_NONE>,
 417                                         <132 IRQ_TYPE_NONE>,
 418                                         <133 IRQ_TYPE_NONE>,
 419                                         <134 IRQ_TYPE_NONE>,
 420                                         <135 IRQ_TYPE_NONE>,
 421                                         <136 IRQ_TYPE_NONE>,
 422                                         <137 IRQ_TYPE_NONE>,
 423                                         <138 IRQ_TYPE_NONE>,
 424                                         <139 IRQ_TYPE_NONE>;
 425                                 };
 426
 427                                 rtc@11d {
 428                                         compatible = "qcom,pm8921-rtc";
 429                                         interrupt-parent = <&pmicintc>;
 430                                         interrupts = <39 1>;
 431                                         reg = <0x11d>;
 432                                         allow-set-time;
 433                                 };
 434
 435                                 pwrkey@1c {
 436                                         compatible = "qcom,pm8921-pwrkey";
 437                                         reg = <0x1c>;
 438                                         interrupt-parent = <&pmicintc>;
 439                                         interrupts = <50 1>, <51 1>;
 440                                         debounce = <15625>;
 441                                         pull-up;
 442                                 };
 443                         };
 444                 };
 445
 446                 gcc: clock-controller@900000 {
 447                         compatible = "qcom,gcc-apq8064";
 448                         reg = <0x00900000 0x4000>;
 449                         #clock-cells = <1>;
 450                         #reset-cells = <1>;
 451                 };
 452
 453                 lcc: clock-controller@28000000 {
 454                         compatible = "qcom,lcc-apq8064";
 455                         reg = <0x28000000 0x1000>;
 456                         #clock-cells = <1>;
 457                         #reset-cells = <1>;
 458                 };
 459
 460                 mmcc: clock-controller@4000000 {
 461                         compatible = "qcom,mmcc-apq8064";
 462                         reg = <0x4000000 0x1000>;
 463                         #clock-cells = <1>;
 464                         #reset-cells = <1>;
 465                 };
 466
 467                 l2cc: clock-controller@2011000 {
 468                         compatible      = "syscon";
 469                         reg             = <0x2011000 0x1000>;
 470                 };
 471
 472                 rpm@108000 {
 473                         compatible      = "qcom,rpm-apq8064";
 474                         reg             = <0x108000 0x1000>;
 475                         qcom,ipc        = <&l2cc 0x8 2>;
 476
 477                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 478                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 479                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 480                         interrupt-names = "ack", "err", "wakeup";
 481
 482                         regulators {
 483                                 compatible = "qcom,rpm-pm8921-regulators";
 484
 485                                 pm8921_hdmi_switch: hdmi-switch {
 486                                         bias-pull-down;
 487                                 };
 488                         };
 489                 };
 490
 491                 usb1_phy: phy@12500000 {
 492                         compatible      = "qcom,usb-otg-ci";
 493                         reg             = <0x12500000 0x400>;
 494                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 495                         status          = "disabled";
 496                         dr_mode         = "host";
 497
 498                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 499                                           <&gcc USB_HS1_H_CLK>;
 500                         clock-names     = "core", "iface";
 501
 502                         resets          = <&gcc USB_HS1_RESET>;
 503                         reset-names     = "link";
 504                 };
 505
 506                 usb3_phy: phy@12520000 {
 507                         compatible      = "qcom,usb-otg-ci";
 508                         reg             = <0x12520000 0x400>;
 509                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 510                         status          = "disabled";
 511                         dr_mode         = "host";
 512
 513                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 514                                           <&gcc USB_HS3_H_CLK>;
 515                         clock-names     = "core", "iface";
 516
 517                         resets          = <&gcc USB_HS3_RESET>;
 518                         reset-names     = "link";
 519                 };
 520
 521                 usb4_phy: phy@12530000 {
 522                         compatible      = "qcom,usb-otg-ci";
 523                         reg             = <0x12530000 0x400>;
 524                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 525                         status          = "disabled";
 526                         dr_mode         = "host";
 527
 528                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 529                                           <&gcc USB_HS4_H_CLK>;
 530                         clock-names     = "core", "iface";
 531
 532                         resets          = <&gcc USB_HS4_RESET>;
 533                         reset-names     = "link";
 534                 };
 535
 536                 gadget1: gadget@12500000 {
 537                         compatible      = "qcom,ci-hdrc";
 538                         reg             = <0x12500000 0x400>;
 539                         status          = "disabled";
 540                         dr_mode         = "peripheral";
 541                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 542                         usb-phy         = <&usb1_phy>;
 543                 };
 544
 545                 usb1: usb@12500000 {
 546                         compatible      = "qcom,ehci-host";
 547                         reg             = <0x12500000 0x400>;
 548                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 549                         status          = "disabled";
 550                         usb-phy         = <&usb1_phy>;
 551                 };
 552
 553                 usb3: usb@12520000 {
 554                         compatible      = "qcom,ehci-host";
 555                         reg             = <0x12520000 0x400>;
 556                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 557                         status          = "disabled";
 558                         usb-phy         = <&usb3_phy>;
 559                 };
 560
 561                 usb4: usb@12530000 {
 562                         compatible      = "qcom,ehci-host";
 563                         reg             = <0x12530000 0x400>;
 564                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 565                         status          = "disabled";
 566                         usb-phy         = <&usb4_phy>;
 567                 };
 568
 569                 sata_phy0: phy@1b400000 {
 570                         compatible      = "qcom,apq8064-sata-phy";
 571                         status          = "disabled";
 572                         reg             = <0x1b400000 0x200>;
 573                         reg-names       = "phy_mem";
 574                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 575                         clock-names     = "cfg";
 576                         #phy-cells      = <0>;
 577                 };
 578
 579                 sata0: sata@29000000 {
 580                         compatible              = "generic-ahci";
 581                         status                  = "disabled";
 582                         reg                     = <0x29000000 0x180>;
 583                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 584
 585                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 586                                                 <&gcc SATA_H_CLK>,
 587                                                 <&gcc SATA_A_CLK>,
 588                                                 <&gcc SATA_RXOOB_CLK>,
 589                                                 <&gcc SATA_PMALIVE_CLK>;
 590                         clock-names             = "slave_iface",
 591                                                 "iface",
 592                                                 "bus",
 593                                                 "rxoob",
 594                                                 "core_pmalive";
 595
 596                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 597                                                 <&gcc SATA_PMALIVE_CLK>;
 598                         assigned-clock-rates    = <100000000>, <100000000>;
 599
 600                         phys                    = <&sata_phy0>;
 601                         phy-names               = "sata-phy";
 602                 };
 603
 604                 /* Temporary fixed regulator */
 605                 sdcc1bam:dma@12402000{
 606                         compatible = "qcom,bam-v1.3.0";
 607                         reg = <0x12402000 0x8000>;
 608                         interrupts = <0 98 0>;
 609                         clocks = <&gcc SDC1_H_CLK>;
 610                         clock-names = "bam_clk";
 611                         #dma-cells = <1>;
 612                         qcom,ee = <0>;
 613                 };
 614
 615                 sdcc3bam:dma@12182000{
 616                         compatible = "qcom,bam-v1.3.0";
 617                         reg = <0x12182000 0x8000>;
 618                         interrupts = <0 96 0>;
 619                         clocks = <&gcc SDC3_H_CLK>;
 620                         clock-names = "bam_clk";
 621                         #dma-cells = <1>;
 622                         qcom,ee = <0>;
 623                 };
 624
 625                 sdcc4bam:dma@121c2000{
 626                         compatible = "qcom,bam-v1.3.0";
 627                         reg = <0x121c2000 0x8000>;
 628                         interrupts = <0 95 0>;
 629                         clocks = <&gcc SDC4_H_CLK>;
 630                         clock-names = "bam_clk";
 631                         #dma-cells = <1>;
 632                         qcom,ee = <0>;
 633                 };
 634
 635                 amba {
 636                         compatible = "arm,amba-bus";
 637                         #address-cells = <1>;
 638                         #size-cells = <1>;
 639                         ranges;
 640                         sdcc1: sdcc@12400000 {
 641                                 status          = "disabled";
 642                                 compatible      = "arm,pl18x", "arm,primecell";
 643                                 arm,primecell-periphid = <0x00051180>;
 644                                 reg             = <0x12400000 0x2000>;
 645                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 646                                 interrupt-names = "cmd_irq";
 647                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 648                                 clock-names     = "mclk", "apb_pclk";
 649                                 bus-width       = <8>;
 650                                 max-frequency   = <96000000>;
 651                                 non-removable;
 652                                 cap-sd-highspeed;
 653                                 cap-mmc-highspeed;
 654                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 655                                 dma-names = "tx", "rx";
 656                         };
 657
 658                         sdcc3: sdcc@12180000 {
 659                                 compatible      = "arm,pl18x", "arm,primecell";
 660                                 arm,primecell-periphid = <0x00051180>;
 661                                 status          = "disabled";
 662                                 reg             = <0x12180000 0x2000>;
 663                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 664                                 interrupt-names = "cmd_irq";
 665                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 666                                 clock-names     = "mclk", "apb_pclk";
 667                                 bus-width       = <4>;
 668                                 cap-sd-highspeed;
 669                                 cap-mmc-highspeed;
 670                                 max-frequency   = <192000000>;
 671                                 no-1-8-v;
 672                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 673                                 dma-names = "tx", "rx";
 674                         };
 675
 676                         sdcc4: sdcc@121c0000 {
 677                                 compatible      = "arm,pl18x", "arm,primecell";
 678                                 arm,primecell-periphid = <0x00051180>;
 679                                 status          = "disabled";
 680                                 reg             = <0x121c0000 0x2000>;
 681                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 682                                 interrupt-names = "cmd_irq";
 683                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 684                                 clock-names     = "mclk", "apb_pclk";
 685                                 bus-width       = <4>;
 686                                 cap-sd-highspeed;
 687                                 cap-mmc-highspeed;
 688                                 max-frequency   = <48000000>;
 689                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 690                                 dma-names = "tx", "rx";
 691                                 pinctrl-names = "default";
 692                                 pinctrl-0 = <&sdc4_gpios>;
 693                         };
 694                 };
 695
 696                 tcsr: syscon@1a400000 {
 697                         compatible = "qcom,tcsr-apq8064", "syscon";
 698                         reg = <0x1a400000 0x100>;
 699                 };
 700         };
 701 };