arch/arm/boot/dts/lcd-b080xan03.0-mipi.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * Licensed under GPLv2 or later.
   4  * arch/arm/boot/dts/lcd-b080xan03.0-mipi.dtsi
   5  * author: chenyf@rock-chips.com
   6  * create date: 2014-09-11
   7  * lcd model: b080xan03.0
   8  * resolution: 768 X 1024
   9  * mipi channel: single
  10  */
  11
  12 / {
  13                 /* about mipi */
  14                 disp_mipi_init: mipi_dsi_init{
  15                                         compatible = "rockchip,mipi_dsi_init";
  16                                         rockchip,screen_init    = <0>;
  17                                         rockchip,dsi_lane               = <4>;
  18                                         rockchip,dsi_hs_clk             = <528>;
  19                                         rockchip,mipi_dsi_num   = <1>;
  20                 };
  21                 disp_mipi_power_ctr: mipi_power_ctr {
  22                                         compatible = "rockchip,mipi_power_ctr";
  23                                         mipi_lcd_rst:mipi_lcd_rst{
  24                                                         compatible = "rockchip,lcd_rst";
  25                                                         rockchip,gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>;
  26                                                         rockchip,delay = <20>;
  27                                         };
  28                                 /*      mipi_lcd_en:mipi_lcd_en {
  29                                                         compatible = "rockchip,lcd_en";
  30                                                         rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
  31                                                         rockchip,delay = <100>;
  32                                         };*/
  33                 };
  34                 disp_mipi_init_cmds: screen-on-cmds {
  35                                         compatible = "rockchip,screen-on-cmds";
  36                                         /*rockchip,cmd_debug = <1>;
  37                                         rockchip,on-cmds1 {
  38                                                         compatible = "rockchip,on-cmds";
  39                                                         rockchip,cmd_type = <HSDT>;
  40                                                         rockchip,dsi_id = <2>;
  41                                                         rockchip,cmd = <0xb0 0x02>;
  42                                                         rockchip,cmd_delay = <0>;
  43                                         };
  44                                         */
  45                 };
  46
  47
  48                 disp_timings: display-timings {
  49                         native-mode = <&timing0>;
  50                         compatible = "rockchip,display-timings";
  51                         timing0: timing0 {
  52                                 screen-type = <SCREEN_MIPI>;
  53                                 lvds-format = <LVDS_8BIT_2>;
  54                                 out-face    = <OUT_P666>;
  55                                 clock-frequency = <67000000>;
  56                                 hactive = <768>;
  57                                 vactive = <1024>;
  58                                 hback-porch = <56>;
  59                                 hfront-porch = <60>;
  60                                 vback-porch = <30>;
  61                                 vfront-porch = <36>;
  62                                 hsync-len = <64>;
  63                                 vsync-len = <14>;
  64
  65                                 /*
  66                                 hactive = <1024>;
  67                                 vactive = <768>;
  68                                 hback-porch = <56>;
  69                                 hfront-porch = <60>;
  70                                 vback-porch = <30>;
  71                                 vfront-porch = <36>;
  72                                 hsync-len = <64>;
  73                                 vsync-len = <14>;
  74                                 */
  75                                 hsync-active = <0>;
  76                                 vsync-active = <0>;
  77                                 de-active = <0>;
  78                                 pixelclk-active = <0>;
  79                                 swap-rb = <0>;
  80                                 swap-rg = <0>;
  81                                 swap-gb = <0>;
  82                         };
  83                };
  84 };