arch/arm/boot/dts/armada-xp-mv78260.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  *
  12  * Contains definitions specific to the Armada XP MV78260 SoC that are not
  13  * common to all Armada XP SoCs.
  14  */
  15
  16 /include/ "armada-xp.dtsi"
  17
  18 / {
  19         model = "Marvell Armada XP MV78260 SoC";
  20         compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "marvell,sheeva-v7";
  35                         reg = <0>;
  36                         clocks = <&cpuclk 0>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "marvell,sheeva-v7";
  42                         reg = <1>;
  43                         clocks = <&cpuclk 1>;
  44                 };
  45         };
  46
  47         soc {
  48                 internal-regs {
  49                         pinctrl {
  50                                 compatible = "marvell,mv78260-pinctrl";
  51                                 reg = <0x18000 0x38>;
  52
  53                                 sdio_pins: sdio-pins {
  54                                         marvell,pins = "mpp30", "mpp31", "mpp32",
  55                                                        "mpp33", "mpp34", "mpp35";
  56                                         marvell,function = "sd0";
  57                                 };
  58                         };
  59
  60                         gpio0: gpio@18100 {
  61                                 compatible = "marvell,orion-gpio";
  62                                 reg = <0x18100 0x40>;
  63                                 ngpios = <32>;
  64                                 gpio-controller;
  65                                 #gpio-cells = <2>;
  66                                 interrupt-controller;
  67                                 #interrupts-cells = <2>;
  68                                 interrupts = <82>, <83>, <84>, <85>;
  69                         };
  70
  71                         gpio1: gpio@18140 {
  72                                 compatible = "marvell,orion-gpio";
  73                                 reg = <0x18140 0x40>;
  74                                 ngpios = <32>;
  75                                 gpio-controller;
  76                                 #gpio-cells = <2>;
  77                                 interrupt-controller;
  78                                 #interrupts-cells = <2>;
  79                                 interrupts = <87>, <88>, <89>, <90>;
  80                         };
  81
  82                         gpio2: gpio@18180 {
  83                                 compatible = "marvell,orion-gpio";
  84                                 reg = <0x18180 0x40>;
  85                                 ngpios = <3>;
  86                                 gpio-controller;
  87                                 #gpio-cells = <2>;
  88                                 interrupt-controller;
  89                                 #interrupts-cells = <2>;
  90                                 interrupts = <91>;
  91                         };
  92
  93                         ethernet@34000 {
  94                                 compatible = "marvell,armada-370-neta";
  95                                 reg = <0x34000 0x2500>;
  96                                 interrupts = <14>;
  97                                 clocks = <&gateclk 1>;
  98                                 status = "disabled";
  99                         };
 100
 101                         /*
 102                          * MV78260 has 3 PCIe units Gen2.0: Two units can be
 103                          * configured as x4 or quad x1 lanes. One unit is
 104                          * x4 only.
 105                          */
 106                         pcie-controller {
 107                                 compatible = "marvell,armada-xp-pcie";
 108                                 status = "disabled";
 109                                 device_type = "pci";
 110
 111                                 #address-cells = <3>;
 112                                 #size-cells = <2>;
 113
 114                                 bus-range = <0x00 0xff>;
 115
 116                                 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 117                                         0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
 118                                         0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
 119                                         0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
 120                                         0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
 121                                         0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 122                                         0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
 123                                         0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
 124                                         0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
 125                                         0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 126                                         0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
 127
 128                                 pcie@1,0 {
 129                                         device_type = "pci";
 130                                         assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 131                                         reg = <0x0800 0 0 0 0>;
 132                                         #address-cells = <3>;
 133                                         #size-cells = <2>;
 134                                         #interrupt-cells = <1>;
 135                                         ranges;
 136                                         interrupt-map-mask = <0 0 0 0>;
 137                                         interrupt-map = <0 0 0 0 &mpic 58>;
 138                                         marvell,pcie-port = <0>;
 139                                         marvell,pcie-lane = <0>;
 140                                         clocks = <&gateclk 5>;
 141                                         status = "disabled";
 142                                 };
 143
 144                                 pcie@2,0 {
 145                                         device_type = "pci";
 146                                         assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 147                                         reg = <0x1000 0 0 0 0>;
 148                                         #address-cells = <3>;
 149                                         #size-cells = <2>;
 150                                         #interrupt-cells = <1>;
 151                                         ranges;
 152                                         interrupt-map-mask = <0 0 0 0>;
 153                                         interrupt-map = <0 0 0 0 &mpic 59>;
 154                                         marvell,pcie-port = <0>;
 155                                         marvell,pcie-lane = <1>;
 156                                         clocks = <&gateclk 6>;
 157                                         status = "disabled";
 158                                 };
 159
 160                                 pcie@3,0 {
 161                                         device_type = "pci";
 162                                         assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 163                                         reg = <0x1800 0 0 0 0>;
 164                                         #address-cells = <3>;
 165                                         #size-cells = <2>;
 166                                         #interrupt-cells = <1>;
 167                                         ranges;
 168                                         interrupt-map-mask = <0 0 0 0>;
 169                                         interrupt-map = <0 0 0 0 &mpic 60>;
 170                                         marvell,pcie-port = <0>;
 171                                         marvell,pcie-lane = <2>;
 172                                         clocks = <&gateclk 7>;
 173                                         status = "disabled";
 174                                 };
 175
 176                                 pcie@4,0 {
 177                                         device_type = "pci";
 178                                         assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 179                                         reg = <0x2000 0 0 0 0>;
 180                                         #address-cells = <3>;
 181                                         #size-cells = <2>;
 182                                         #interrupt-cells = <1>;
 183                                         ranges;
 184                                         interrupt-map-mask = <0 0 0 0>;
 185                                         interrupt-map = <0 0 0 0 &mpic 61>;
 186                                         marvell,pcie-port = <0>;
 187                                         marvell,pcie-lane = <3>;
 188                                         clocks = <&gateclk 8>;
 189                                         status = "disabled";
 190                                 };
 191
 192                                 pcie@5,0 {
 193                                         device_type = "pci";
 194                                         assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 195                                         reg = <0x2800 0 0 0 0>;
 196                                         #address-cells = <3>;
 197                                         #size-cells = <2>;
 198                                         #interrupt-cells = <1>;
 199                                         ranges;
 200                                         interrupt-map-mask = <0 0 0 0>;
 201                                         interrupt-map = <0 0 0 0 &mpic 62>;
 202                                         marvell,pcie-port = <1>;
 203                                         marvell,pcie-lane = <0>;
 204                                         clocks = <&gateclk 9>;
 205                                         status = "disabled";
 206                                 };
 207
 208                                 pcie@6,0 {
 209                                         device_type = "pci";
 210                                         assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
 211                                         reg = <0x3000 0 0 0 0>;
 212                                         #address-cells = <3>;
 213                                         #size-cells = <2>;
 214                                         #interrupt-cells = <1>;
 215                                         ranges;
 216                                         interrupt-map-mask = <0 0 0 0>;
 217                                         interrupt-map = <0 0 0 0 &mpic 63>;
 218                                         marvell,pcie-port = <1>;
 219                                         marvell,pcie-lane = <1>;
 220                                         clocks = <&gateclk 10>;
 221                                         status = "disabled";
 222                                 };
 223
 224                                 pcie@7,0 {
 225                                         device_type = "pci";
 226                                         assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
 227                                         reg = <0x3800 0 0 0 0>;
 228                                         #address-cells = <3>;
 229                                         #size-cells = <2>;
 230                                         #interrupt-cells = <1>;
 231                                         ranges;
 232                                         interrupt-map-mask = <0 0 0 0>;
 233                                         interrupt-map = <0 0 0 0 &mpic 64>;
 234                                         marvell,pcie-port = <1>;
 235                                         marvell,pcie-lane = <2>;
 236                                         clocks = <&gateclk 11>;
 237                                         status = "disabled";
 238                                 };
 239
 240                                 pcie@8,0 {
 241                                         device_type = "pci";
 242                                         assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
 243                                         reg = <0x4000 0 0 0 0>;
 244                                         #address-cells = <3>;
 245                                         #size-cells = <2>;
 246                                         #interrupt-cells = <1>;
 247                                         ranges;
 248                                         interrupt-map-mask = <0 0 0 0>;
 249                                         interrupt-map = <0 0 0 0 &mpic 65>;
 250                                         marvell,pcie-port = <1>;
 251                                         marvell,pcie-lane = <3>;
 252                                         clocks = <&gateclk 12>;
 253                                         status = "disabled";
 254                                 };
 255
 256                                 pcie@9,0 {
 257                                         device_type = "pci";
 258                                         assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 259                                         reg = <0x4800 0 0 0 0>;
 260                                         #address-cells = <3>;
 261                                         #size-cells = <2>;
 262                                         #interrupt-cells = <1>;
 263                                         ranges;
 264                                         interrupt-map-mask = <0 0 0 0>;
 265                                         interrupt-map = <0 0 0 0 &mpic 99>;
 266                                         marvell,pcie-port = <2>;
 267                                         marvell,pcie-lane = <0>;
 268                                         clocks = <&gateclk 26>;
 269                                         status = "disabled";
 270                                 };
 271                         };
 272                 };
 273         };
 274 };