4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_SUPPORTS_ATOMIC_RMW
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SMP_IDLE_THREAD
20 select GENERIC_IDLE_POLL_SETUP
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_DEBUG_KMEMLEAK
31 select HAVE_DMA_API_DEBUG
33 select HAVE_DMA_CONTIGUOUS if MMU
34 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
35 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
36 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
37 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
38 select HAVE_GENERIC_DMA_COHERENT
39 select HAVE_GENERIC_HARDIRQS
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZMA
45 select HAVE_KERNEL_LZO
47 select HAVE_KPROBES if !XIP_KERNEL
48 select HAVE_KRETPROBES if (HAVE_KPROBES)
50 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
51 select HAVE_PERF_EVENTS
52 select HAVE_REGS_AND_STACK_ACCESS_API
53 select HAVE_SYSCALL_TRACEPOINTS
56 select PERF_USE_VMALLOC
58 select SYS_SUPPORTS_APM_EMULATION
59 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
60 select MODULES_USE_ELF_REL
61 select CLONE_BACKWARDS
62 select OLD_SIGSUSPEND3
64 select HAVE_CONTEXT_TRACKING
66 The ARM series is a line of low-power-consumption RISC chip designs
67 licensed by ARM Ltd and targeted at embedded applications and
68 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
69 manufactured, but legacy ARM-based PC hardware remains popular in
70 Europe. There is an ARM Linux project with a web page at
71 <http://www.arm.linux.org.uk/>.
73 config ARM_HAS_SG_CHAIN
76 config NEED_SG_DMA_LENGTH
79 config ARM_DMA_USE_IOMMU
81 select ARM_HAS_SG_CHAIN
82 select NEED_SG_DMA_LENGTH
86 config ARM_DMA_IOMMU_ALIGNMENT
87 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
91 DMA mapping framework by default aligns all buffers to the smallest
92 PAGE_SIZE order which is greater than or equal to the requested buffer
93 size. This works well for buffers up to a few hundreds kilobytes, but
94 for larger buffers it just a waste of address space. Drivers which has
95 relatively small addressing window (like 64Mib) might run out of
96 virtual space with just a few allocations.
98 With this parameter you can specify the maximum PAGE_SIZE order for
99 DMA IOMMU buffers. Larger buffers will be aligned only to this
100 specified order. The order is expressed as a power of two multiplied
108 config MIGHT_HAVE_PCI
111 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors. This must be two pages
220 config ARM_PATCH_PHYS_VIRT
221 bool "Patch physical to virtual translations at runtime" if EMBEDDED
223 depends on !XIP_KERNEL && MMU
224 depends on !ARCH_REALVIEW || !SPARSEMEM
226 Patch phys-to-virt and virt-to-phys translation functions at
227 boot and module load time according to the position of the
228 kernel in system memory.
230 This can only be used with non-XIP MMU kernels where the base
231 of physical memory is at a 16MB boundary.
233 Only disable this option if you know that you do not require
234 this feature (eg, building a kernel for a single machine) and
235 you need to shrink the kernel to the minimal size.
237 config NEED_MACH_GPIO_H
240 Select this when mach/gpio.h is required to provide special
241 definitions for this platform. The need for mach/gpio.h should
242 be avoided when possible.
244 config NEED_MACH_IO_H
247 Select this when mach/io.h is required to provide special
248 definitions for this platform. The need for mach/io.h should
249 be avoided when possible.
251 config NEED_MACH_MEMORY_H
254 Select this when mach/memory.h is required to provide special
255 definitions for this platform. The need for mach/memory.h should
256 be avoided when possible.
259 hex "Physical address of main memory" if MMU
260 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
261 default DRAM_BASE if !MMU
263 Please provide the physical address corresponding to the
264 location of main memory in your system.
270 source "init/Kconfig"
272 source "kernel/Kconfig.freezer"
277 bool "MMU-based Paged Memory Management Support"
280 Select if you want MMU-based virtualised addressing space
281 support by paged memory management. If unsure, say 'Y'.
284 # The "ARM system type" choice list is ordered alphabetically by option
285 # text. Please add new entries in the option alphabetic order.
288 prompt "ARM system type"
289 default ARCH_VERSATILE if !MMU
290 default ARCH_MULTIPLATFORM if MMU
292 config ARCH_MULTIPLATFORM
293 bool "Allow multiple platforms to be selected"
295 select ARM_PATCH_PHYS_VIRT
298 select MULTI_IRQ_HANDLER
302 config ARCH_INTEGRATOR
303 bool "ARM Ltd. Integrator family"
304 select ARCH_HAS_CPUFREQ
307 select COMMON_CLK_VERSATILE
308 select GENERIC_CLOCKEVENTS
311 select MULTI_IRQ_HANDLER
312 select NEED_MACH_MEMORY_H
313 select PLAT_VERSATILE
315 select VERSATILE_FPGA_IRQ
317 Support for ARM's Integrator platform.
320 bool "ARM Ltd. RealView family"
321 select ARCH_WANT_OPTIONAL_GPIOLIB
323 select ARM_TIMER_SP804
325 select COMMON_CLK_VERSATILE
326 select GENERIC_CLOCKEVENTS
327 select GPIO_PL061 if GPIOLIB
329 select NEED_MACH_MEMORY_H
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
333 This enables support for ARM Ltd RealView boards.
335 config ARCH_VERSATILE
336 bool "ARM Ltd. Versatile family"
337 select ARCH_WANT_OPTIONAL_GPIOLIB
339 select ARM_TIMER_SP804
342 select GENERIC_CLOCKEVENTS
343 select HAVE_MACH_CLKDEV
345 select PLAT_VERSATILE
346 select PLAT_VERSATILE_CLCD
347 select PLAT_VERSATILE_CLOCK
348 select VERSATILE_FPGA_IRQ
350 This enables support for ARM Ltd Versatile board.
354 select ARCH_REQUIRE_GPIOLIB
358 select NEED_MACH_GPIO_H
359 select NEED_MACH_IO_H if PCCARD
361 select PINCTRL_AT91 if USE_OF
363 This enables support for systems based on Atmel
364 AT91RM9200 and AT91SAM9* processors.
367 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
374 select MULTI_IRQ_HANDLER
375 select NEED_MACH_MEMORY_H
378 Support for Cirrus Logic 711x/721x/731x based boards.
381 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
383 select ARCH_USES_GETTIMEOFFSET
384 select NEED_MACH_GPIO_H
387 Support for the Cortina Systems Gemini family SoCs
391 select ARCH_USES_GETTIMEOFFSET
394 select NEED_MACH_IO_H
395 select NEED_MACH_MEMORY_H
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
405 select ARCH_HAS_HOLES_MEMORYMODEL
406 select ARCH_REQUIRE_GPIOLIB
407 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
422 select NEED_MACH_IO_H if !MMU
423 select NEED_MACH_MEMORY_H
425 Support for systems based on the DC21285 companion chip
426 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
429 bool "Hilscher NetX based"
433 select GENERIC_CLOCKEVENTS
435 This enables support for systems based on the Hilscher NetX Soc
440 select ARCH_SUPPORTS_MSI
442 select NEED_MACH_MEMORY_H
443 select NEED_RET_TO_USER
448 Support for Intel's IOP13XX (XScale) family of processors.
453 select ARCH_REQUIRE_GPIOLIB
455 select NEED_MACH_GPIO_H
456 select NEED_RET_TO_USER
460 Support for Intel's 80219 and IOP32X (XScale) family of
466 select ARCH_REQUIRE_GPIOLIB
468 select NEED_MACH_GPIO_H
469 select NEED_RET_TO_USER
473 Support for Intel's IOP33X (XScale) family of processors.
478 select ARCH_HAS_DMA_SET_COHERENT_MASK
479 select ARCH_SUPPORTS_BIG_ENDIAN
480 select ARCH_REQUIRE_GPIOLIB
483 select DMABOUNCE if PCI
484 select GENERIC_CLOCKEVENTS
485 select MIGHT_HAVE_PCI
486 select NEED_MACH_IO_H
487 select USB_EHCI_BIG_ENDIAN_MMIO
488 select USB_EHCI_BIG_ENDIAN_DESC
490 Support for Intel's IXP4XX (XScale) family of processors.
494 select ARCH_REQUIRE_GPIOLIB
496 select GENERIC_CLOCKEVENTS
497 select MIGHT_HAVE_PCI
500 select PLAT_ORION_LEGACY
501 select USB_ARCH_HAS_EHCI
504 Support for the Marvell Dove SoC 88AP510
507 bool "Marvell Kirkwood"
508 select ARCH_REQUIRE_GPIOLIB
510 select GENERIC_CLOCKEVENTS
514 select PINCTRL_KIRKWOOD
515 select PLAT_ORION_LEGACY
518 Support for the following Marvell Kirkwood series SoCs:
519 88F6180, 88F6192 and 88F6281.
522 bool "Marvell MV78xx0"
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
527 select PLAT_ORION_LEGACY
530 Support for the following Marvell MV78xx0 series SoCs:
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
543 Support for the following Marvell Orion 5x series SoCs:
544 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
545 Orion-2 (5281), Orion-1-90 (6183).
548 bool "Marvell PXA168/910/MMP2"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_ALLOCATOR
553 select GENERIC_CLOCKEVENTS
556 select NEED_MACH_GPIO_H
561 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
564 bool "Micrel/Kendin KS8695"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
569 select NEED_MACH_MEMORY_H
571 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
572 System-on-Chip devices.
575 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
592 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
600 select USB_ARCH_HAS_OHCI
603 Support for the NXP LPC32XX family of processors
606 bool "PXA2xx/PXA3xx-based"
608 select ARCH_HAS_CPUFREQ
610 select ARCH_REQUIRE_GPIOLIB
611 select ARM_CPU_SUSPEND if PM
615 select GENERIC_CLOCKEVENTS
618 select MULTI_IRQ_HANDLER
619 select NEED_MACH_GPIO_H
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
641 select GENERIC_CLOCKEVENTS
642 select HAVE_ARM_SCU if SMP
643 select HAVE_ARM_TWD if LOCAL_TIMERS
645 select HAVE_MACH_CLKDEV
647 select MIGHT_HAVE_CACHE_L2X0
648 select MULTI_IRQ_HANDLER
649 select NEED_MACH_MEMORY_H
651 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
652 select PM_GENERIC_DOMAINS if PM
655 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
660 select ARCH_MAY_HAVE_PC_FDC
661 select ARCH_SPARSEMEM_ENABLE
662 select ARCH_USES_GETTIMEOFFSET
665 select HAVE_PATA_PLATFORM
667 select NEED_MACH_IO_H
668 select NEED_MACH_MEMORY_H
672 On the Acorn Risc-PC, Linux can support the internal IDE disk and
673 CD-ROM interface, serial and parallel port, and the floppy drive.
677 select ARCH_HAS_CPUFREQ
679 select ARCH_REQUIRE_GPIOLIB
680 select ARCH_SPARSEMEM_ENABLE
685 select GENERIC_CLOCKEVENTS
688 select NEED_MACH_GPIO_H
689 select NEED_MACH_MEMORY_H
692 Support for StrongARM 11x0 based boards.
695 bool "Samsung S3C24XX SoCs"
696 select ARCH_HAS_CPUFREQ
697 select ARCH_REQUIRE_GPIOLIB
700 select GENERIC_CLOCKEVENTS
702 select HAVE_S3C2410_I2C if I2C
703 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select HAVE_S3C_RTC if RTC_CLASS
705 select MULTI_IRQ_HANDLER
706 select NEED_MACH_GPIO_H
707 select NEED_MACH_IO_H
709 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
710 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
711 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
712 Samsung SMDK2410 development board (and derivatives).
715 bool "Samsung S3C64XX"
716 select ARCH_HAS_CPUFREQ
717 select ARCH_REQUIRE_GPIOLIB
722 select GENERIC_CLOCKEVENTS
724 select HAVE_S3C2410_I2C if I2C
725 select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 select NEED_MACH_GPIO_H
731 select S3C_GPIO_TRACK
732 select SAMSUNG_CLKSRC
733 select SAMSUNG_GPIOLIB_4BIT
734 select SAMSUNG_IRQ_VIC_TIMER
735 select USB_ARCH_HAS_OHCI
737 Samsung S3C64XX series based systems
740 bool "Samsung S5P6440 S5P6450"
744 select GENERIC_CLOCKEVENTS
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
748 select HAVE_S3C_RTC if RTC_CLASS
749 select NEED_MACH_GPIO_H
751 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
755 bool "Samsung S5PC100"
756 select ARCH_REQUIRE_GPIOLIB
760 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select HAVE_S3C_RTC if RTC_CLASS
765 select NEED_MACH_GPIO_H
767 Samsung S5PC100 series based systems
770 bool "Samsung S5PV210/S5PC110"
771 select ARCH_HAS_CPUFREQ
772 select ARCH_HAS_HOLES_MEMORYMODEL
773 select ARCH_SPARSEMEM_ENABLE
777 select GENERIC_CLOCKEVENTS
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG
781 select HAVE_S3C_RTC if RTC_CLASS
782 select NEED_MACH_GPIO_H
783 select NEED_MACH_MEMORY_H
785 Samsung S5PV210/S5PC110 series based systems
788 bool "Samsung EXYNOS"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_SPARSEMEM_ENABLE
795 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select HAVE_S3C_RTC if RTC_CLASS
800 select NEED_MACH_GPIO_H
801 select NEED_MACH_MEMORY_H
803 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
807 select ARCH_USES_GETTIMEOFFSET
811 select NEED_MACH_MEMORY_H
816 Support for the StrongARM based Digital DNARD machine, also known
817 as "Shark" (<http://www.shark-linux.de/shark.html>).
820 bool "ST-Ericsson U300 Series"
822 select ARCH_REQUIRE_GPIOLIB
824 select ARM_PATCH_PHYS_VIRT
830 select GENERIC_CLOCKEVENTS
834 Support for ST-Ericsson U300 series mobile platforms.
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_REQUIRE_GPIOLIB
841 select GENERIC_ALLOCATOR
842 select GENERIC_CLOCKEVENTS
843 select GENERIC_IRQ_CHIP
845 select NEED_MACH_GPIO_H
849 Support for TI's DaVinci platform.
854 select ARCH_HAS_CPUFREQ
855 select ARCH_HAS_HOLES_MEMORYMODEL
857 select ARCH_REQUIRE_GPIOLIB
860 select GENERIC_CLOCKEVENTS
861 select GENERIC_IRQ_CHIP
865 select NEED_MACH_IO_H if PCCARD
866 select NEED_MACH_MEMORY_H
868 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
872 menu "Multiple platform selection"
873 depends on ARCH_MULTIPLATFORM
875 comment "CPU Core family selection"
878 bool "ARMv4 based platforms (FA526, StrongARM)"
879 depends on !ARCH_MULTI_V6_V7
880 select ARCH_MULTI_V4_V5
882 config ARCH_MULTI_V4T
883 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
884 depends on !ARCH_MULTI_V6_V7
885 select ARCH_MULTI_V4_V5
888 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
892 config ARCH_MULTI_V4_V5
896 bool "ARMv6 based platforms (ARM11)"
897 select ARCH_MULTI_V6_V7
901 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
903 select ARCH_MULTI_V6_V7
906 config ARCH_MULTI_V6_V7
909 config ARCH_MULTI_CPU_AUTO
910 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
916 # This is sorted alphabetically by mach-* pathname. However, plat-*
917 # Kconfigs may be included either alphabetically (according to the
918 # plat- suffix) or along side the corresponding mach-* source.
920 source "arch/arm/mach-mvebu/Kconfig"
922 source "arch/arm/mach-at91/Kconfig"
924 source "arch/arm/mach-bcm/Kconfig"
926 source "arch/arm/mach-bcm2835/Kconfig"
928 source "arch/arm/mach-clps711x/Kconfig"
930 source "arch/arm/mach-cns3xxx/Kconfig"
932 source "arch/arm/mach-davinci/Kconfig"
934 source "arch/arm/mach-dove/Kconfig"
936 source "arch/arm/mach-ep93xx/Kconfig"
938 source "arch/arm/mach-footbridge/Kconfig"
940 source "arch/arm/mach-gemini/Kconfig"
942 source "arch/arm/mach-highbank/Kconfig"
944 source "arch/arm/mach-integrator/Kconfig"
946 source "arch/arm/mach-iop32x/Kconfig"
948 source "arch/arm/mach-iop33x/Kconfig"
950 source "arch/arm/mach-iop13xx/Kconfig"
952 source "arch/arm/mach-ixp4xx/Kconfig"
954 source "arch/arm/mach-kirkwood/Kconfig"
956 source "arch/arm/mach-ks8695/Kconfig"
958 source "arch/arm/mach-msm/Kconfig"
960 source "arch/arm/mach-mv78xx0/Kconfig"
962 source "arch/arm/mach-imx/Kconfig"
964 source "arch/arm/mach-mxs/Kconfig"
966 source "arch/arm/mach-netx/Kconfig"
968 source "arch/arm/mach-nomadik/Kconfig"
970 source "arch/arm/plat-omap/Kconfig"
972 source "arch/arm/mach-omap1/Kconfig"
974 source "arch/arm/mach-omap2/Kconfig"
976 source "arch/arm/mach-orion5x/Kconfig"
978 source "arch/arm/mach-picoxcell/Kconfig"
980 source "arch/arm/mach-pxa/Kconfig"
981 source "arch/arm/plat-pxa/Kconfig"
983 source "arch/arm/mach-mmp/Kconfig"
985 source "arch/arm/mach-realview/Kconfig"
987 source "arch/arm/mach-sa1100/Kconfig"
989 source "arch/arm/plat-samsung/Kconfig"
991 source "arch/arm/mach-socfpga/Kconfig"
993 source "arch/arm/mach-spear/Kconfig"
995 source "arch/arm/mach-s3c24xx/Kconfig"
998 source "arch/arm/mach-s3c64xx/Kconfig"
1001 source "arch/arm/mach-s5p64x0/Kconfig"
1003 source "arch/arm/mach-s5pc100/Kconfig"
1005 source "arch/arm/mach-s5pv210/Kconfig"
1007 source "arch/arm/mach-exynos/Kconfig"
1009 source "arch/arm/mach-shmobile/Kconfig"
1011 source "arch/arm/mach-sunxi/Kconfig"
1013 source "arch/arm/mach-prima2/Kconfig"
1015 source "arch/arm/mach-tegra/Kconfig"
1017 source "arch/arm/mach-u300/Kconfig"
1019 source "arch/arm/mach-ux500/Kconfig"
1021 source "arch/arm/mach-versatile/Kconfig"
1023 source "arch/arm/mach-vexpress/Kconfig"
1024 source "arch/arm/plat-versatile/Kconfig"
1026 source "arch/arm/mach-virt/Kconfig"
1028 source "arch/arm/mach-vt8500/Kconfig"
1030 source "arch/arm/mach-w90x900/Kconfig"
1032 source "arch/arm/mach-zynq/Kconfig"
1034 # Definitions to make life easier
1040 select GENERIC_CLOCKEVENTS
1046 select GENERIC_IRQ_CHIP
1049 config PLAT_ORION_LEGACY
1056 config PLAT_VERSATILE
1059 config ARM_TIMER_SP804
1062 select CLKSRC_OF if OF
1064 source arch/arm/mm/Kconfig
1068 default 16 if ARCH_EP93XX
1072 bool "Enable iWMMXt support" if !CPU_PJ4
1073 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1074 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1076 Enable support for iWMMXt context switching at run time if
1077 running on a CPU that supports it.
1081 depends on CPU_XSCALE
1084 config MULTI_IRQ_HANDLER
1087 Allow each machine to specify it's own IRQ handler at run time.
1090 source "arch/arm/Kconfig-nommu"
1093 config PJ4B_ERRATA_4742
1094 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1095 depends on CPU_PJ4B && MACH_ARMADA_370
1098 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1099 Event (WFE) IDLE states, a specific timing sensitivity exists between
1100 the retiring WFI/WFE instructions and the newly issued subsequent
1101 instructions. This sensitivity can result in a CPU hang scenario.
1103 The software must insert either a Data Synchronization Barrier (DSB)
1104 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1107 config ARM_ERRATA_326103
1108 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1111 Executing a SWP instruction to read-only memory does not set bit 11
1112 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1113 treat the access as a read, preventing a COW from occurring and
1114 causing the faulting task to livelock.
1116 config ARM_ERRATA_411920
1117 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1118 depends on CPU_V6 || CPU_V6K
1120 Invalidation of the Instruction Cache operation can
1121 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1122 It does not affect the MPCore. This option enables the ARM Ltd.
1123 recommended workaround.
1125 config ARM_ERRATA_430973
1126 bool "ARM errata: Stale prediction on replaced interworking branch"
1129 This option enables the workaround for the 430973 Cortex-A8
1130 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1131 interworking branch is replaced with another code sequence at the
1132 same virtual address, whether due to self-modifying code or virtual
1133 to physical address re-mapping, Cortex-A8 does not recover from the
1134 stale interworking branch prediction. This results in Cortex-A8
1135 executing the new code sequence in the incorrect ARM or Thumb state.
1136 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1137 and also flushes the branch target cache at every context switch.
1138 Note that setting specific bits in the ACTLR register may not be
1139 available in non-secure mode.
1141 config ARM_ERRATA_458693
1142 bool "ARM errata: Processor deadlock when a false hazard is created"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1147 erratum. For very specific sequences of memory operations, it is
1148 possible for a hazard condition intended for a cache line to instead
1149 be incorrectly associated with a different cache line. This false
1150 hazard might then cause a processor deadlock. The workaround enables
1151 the L1 caching of the NEON accesses and disables the PLD instruction
1152 in the ACTLR register. Note that setting specific bits in the ACTLR
1153 register may not be available in non-secure mode.
1155 config ARM_ERRATA_460075
1156 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1158 depends on !ARCH_MULTIPLATFORM
1160 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1161 erratum. Any asynchronous access to the L2 cache may encounter a
1162 situation in which recent store transactions to the L2 cache are lost
1163 and overwritten with stale memory contents from external memory. The
1164 workaround disables the write-allocate mode for the L2 cache via the
1165 ACTLR register. Note that setting specific bits in the ACTLR register
1166 may not be available in non-secure mode.
1168 config ARM_ERRATA_742230
1169 bool "ARM errata: DMB operation may be faulty"
1170 depends on CPU_V7 && SMP
1171 depends on !ARCH_MULTIPLATFORM
1173 This option enables the workaround for the 742230 Cortex-A9
1174 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1175 between two write operations may not ensure the correct visibility
1176 ordering of the two writes. This workaround sets a specific bit in
1177 the diagnostic register of the Cortex-A9 which causes the DMB
1178 instruction to behave as a DSB, ensuring the correct behaviour of
1181 config ARM_ERRATA_742231
1182 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1183 depends on CPU_V7 && SMP
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 742231 Cortex-A9
1187 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1188 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1189 accessing some data located in the same cache line, may get corrupted
1190 data due to bad handling of the address hazard when the line gets
1191 replaced from one of the CPUs at the same time as another CPU is
1192 accessing it. This workaround sets specific bits in the diagnostic
1193 register of the Cortex-A9 which reduces the linefill issuing
1194 capabilities of the processor.
1196 config PL310_ERRATA_588369
1197 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1198 depends on CACHE_L2X0
1200 The PL310 L2 cache controller implements three types of Clean &
1201 Invalidate maintenance operations: by Physical Address
1202 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1203 They are architecturally defined to behave as the execution of a
1204 clean operation followed immediately by an invalidate operation,
1205 both performing to the same memory location. This functionality
1206 is not correctly implemented in PL310 as clean lines are not
1207 invalidated as a result of these operations.
1209 config ARM_ERRATA_643719
1210 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for the 643719 Cortex-A9 (prior to
1214 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1215 register returns zero when it should return one. The workaround
1216 corrects this value, ensuring cache maintenance operations which use
1217 it behave as intended and avoiding data corruption.
1219 config ARM_ERRATA_720789
1220 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1223 This option enables the workaround for the 720789 Cortex-A9 (prior to
1224 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1225 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1226 As a consequence of this erratum, some TLB entries which should be
1227 invalidated are not, resulting in an incoherency in the system page
1228 tables. The workaround changes the TLB flushing routines to invalidate
1229 entries regardless of the ASID.
1231 config PL310_ERRATA_727915
1232 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1233 depends on CACHE_L2X0
1235 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1236 operation (offset 0x7FC). This operation runs in background so that
1237 PL310 can handle normal accesses while it is in progress. Under very
1238 rare circumstances, due to this erratum, write data can be lost when
1239 PL310 treats a cacheable write transaction during a Clean &
1240 Invalidate by Way operation.
1242 config ARM_ERRATA_743622
1243 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 743622 Cortex-A9
1248 (r2p*) erratum. Under very rare conditions, a faulty
1249 optimisation in the Cortex-A9 Store Buffer may lead to data
1250 corruption. This workaround sets a specific bit in the diagnostic
1251 register of the Cortex-A9 which disables the Store Buffer
1252 optimisation, preventing the defect from occurring. This has no
1253 visible impact on the overall performance or power consumption of the
1256 config ARM_ERRATA_751472
1257 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1259 depends on !ARCH_MULTIPLATFORM
1261 This option enables the workaround for the 751472 Cortex-A9 (prior
1262 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1263 completion of a following broadcasted operation if the second
1264 operation is received by a CPU before the ICIALLUIS has completed,
1265 potentially leading to corrupted entries in the cache or TLB.
1267 config PL310_ERRATA_753970
1268 bool "PL310 errata: cache sync operation may be faulty"
1269 depends on CACHE_PL310
1271 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1273 Under some condition the effect of cache sync operation on
1274 the store buffer still remains when the operation completes.
1275 This means that the store buffer is always asked to drain and
1276 this prevents it from merging any further writes. The workaround
1277 is to replace the normal offset of cache sync operation (0x730)
1278 by another offset targeting an unmapped PL310 register 0x740.
1279 This has the same effect as the cache sync operation: store buffer
1280 drain and waiting for all buffers empty.
1282 config ARM_ERRATA_754322
1283 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1286 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1287 r3p*) erratum. A speculative memory access may cause a page table walk
1288 which starts prior to an ASID switch but completes afterwards. This
1289 can populate the micro-TLB with a stale entry which may be hit with
1290 the new ASID. This workaround places two dsb instructions in the mm
1291 switching code so that no page table walks can cross the ASID switch.
1293 config ARM_ERRATA_754327
1294 bool "ARM errata: no automatic Store Buffer drain"
1295 depends on CPU_V7 && SMP
1297 This option enables the workaround for the 754327 Cortex-A9 (prior to
1298 r2p0) erratum. The Store Buffer does not have any automatic draining
1299 mechanism and therefore a livelock may occur if an external agent
1300 continuously polls a memory location waiting to observe an update.
1301 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1302 written polling loops from denying visibility of updates to memory.
1304 config ARM_ERRATA_364296
1305 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1306 depends on CPU_V6 && !SMP
1308 This options enables the workaround for the 364296 ARM1136
1309 r0p2 erratum (possible cache data corruption with
1310 hit-under-miss enabled). It sets the undocumented bit 31 in
1311 the auxiliary control register and the FI bit in the control
1312 register, thus disabling hit-under-miss without putting the
1313 processor into full low interrupt latency mode. ARM11MPCore
1316 config ARM_ERRATA_764369
1317 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1318 depends on CPU_V7 && SMP
1320 This option enables the workaround for erratum 764369
1321 affecting Cortex-A9 MPCore with two or more processors (all
1322 current revisions). Under certain timing circumstances, a data
1323 cache line maintenance operation by MVA targeting an Inner
1324 Shareable memory region may fail to proceed up to either the
1325 Point of Coherency or to the Point of Unification of the
1326 system. This workaround adds a DSB instruction before the
1327 relevant cache maintenance functions and sets a specific bit
1328 in the diagnostic control register of the SCU.
1330 config PL310_ERRATA_769419
1331 bool "PL310 errata: no automatic Store Buffer drain"
1332 depends on CACHE_L2X0
1334 On revisions of the PL310 prior to r3p2, the Store Buffer does
1335 not automatically drain. This can cause normal, non-cacheable
1336 writes to be retained when the memory system is idle, leading
1337 to suboptimal I/O performance for drivers using coherent DMA.
1338 This option adds a write barrier to the cpu_idle loop so that,
1339 on systems with an outer cache, the store buffer is drained
1342 config ARM_ERRATA_775420
1343 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1346 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1347 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1348 operation aborts with MMU exception, it might cause the processor
1349 to deadlock. This workaround puts DSB before executing ISB if
1350 an abort may occur on cache maintenance.
1352 config ARM_ERRATA_798181
1353 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1354 depends on CPU_V7 && SMP
1356 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1357 adequately shooting down all use of the old entries. This
1358 option enables the Linux kernel workaround for this erratum
1359 which sends an IPI to the CPUs that are running the same ASID
1360 as the one being invalidated.
1364 source "arch/arm/common/Kconfig"
1374 Find out whether you have ISA slots on your motherboard. ISA is the
1375 name of a bus system, i.e. the way the CPU talks to the other stuff
1376 inside your box. Other bus systems are PCI, EISA, MicroChannel
1377 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1378 newer boards don't support it. If you have ISA, say Y, otherwise N.
1380 # Select ISA DMA controller support
1385 # Select ISA DMA interface
1390 bool "PCI support" if MIGHT_HAVE_PCI
1392 Find out whether you have a PCI motherboard. PCI is the name of a
1393 bus system, i.e. the way the CPU talks to the other stuff inside
1394 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1395 VESA. If you have PCI, say Y, otherwise N.
1401 config PCI_NANOENGINE
1402 bool "BSE nanoEngine PCI support"
1403 depends on SA1100_NANOENGINE
1405 Enable PCI on the BSE nanoEngine board.
1410 # Select the host bridge type
1411 config PCI_HOST_VIA82C505
1413 depends on PCI && ARCH_SHARK
1416 config PCI_HOST_ITE8152
1418 depends on PCI && MACH_ARMCORE
1422 source "drivers/pci/Kconfig"
1424 source "drivers/pcmcia/Kconfig"
1428 menu "Kernel Features"
1433 This option should be selected by machines which have an SMP-
1436 The only effect of this option is to make the SMP-related
1437 options available to the user for configuration.
1440 bool "Symmetric Multi-Processing"
1441 depends on CPU_V6K || CPU_V7
1442 depends on GENERIC_CLOCKEVENTS
1445 select USE_GENERIC_SMP_HELPERS
1447 This enables support for systems with more than one CPU. If you have
1448 a system with only one CPU, like most personal computers, say N. If
1449 you have a system with more than one CPU, say Y.
1451 If you say N here, the kernel will run on single and multiprocessor
1452 machines, but will use only one CPU of a multiprocessor machine. If
1453 you say Y here, the kernel will run on many, but not all, single
1454 processor machines. On a single processor machine, the kernel will
1455 run faster if you say N here.
1457 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1458 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1459 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1461 If you don't know what to do here, say N.
1464 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1465 depends on SMP && !XIP_KERNEL
1468 SMP kernels contain instructions which fail on non-SMP processors.
1469 Enabling this option allows the kernel to modify itself to make
1470 these instructions safe. Disabling it allows about 1K of space
1473 If you don't know what to do here, say Y.
1475 config ARM_CPU_TOPOLOGY
1476 bool "Support cpu topology definition"
1477 depends on SMP && CPU_V7
1480 Support ARM cpu topology definition. The MPIDR register defines
1481 affinity between processors which is then used to describe the cpu
1482 topology of an ARM System.
1485 bool "Multi-core scheduler support"
1486 depends on ARM_CPU_TOPOLOGY
1488 Multi-core scheduler support improves the CPU scheduler's decision
1489 making when dealing with multi-core CPU chips at a cost of slightly
1490 increased overhead in some places. If unsure say N here.
1493 bool "SMT scheduler support"
1494 depends on ARM_CPU_TOPOLOGY
1496 Improves the CPU scheduler's decision making when dealing with
1497 MultiThreading at a cost of slightly increased overhead in some
1498 places. If unsure say N here.
1500 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1501 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1503 Disables scheduler load-balancing at CPU sched domain level.
1506 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1507 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1509 Experimental scheduler optimizations for heterogeneous platforms.
1510 Attempts to introspectively select task affinity to optimize power
1511 and performance. Basic support for multiple (>2) cpu types is in place,
1512 but it has only been tested with two types of cpus.
1513 There is currently no support for migration of task groups, hence
1514 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1515 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1516 When turned on, this option adds sys/kernel/hmp directory which
1517 contains the following files:
1518 up_threshold - the load average threshold used for up migration
1520 down_threshold - the load average threshold used for down migration
1522 hmp_domains - a list of cpumasks for the present HMP domains,
1523 starting with the 'biggest' and ending with the
1525 Note that both the threshold files can be written at runtime to
1526 control scheduler behaviour.
1528 config SCHED_HMP_PRIO_FILTER
1529 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1530 depends on SCHED_HMP
1532 Enables task priority based HMP migration filter. Any task with
1533 a NICE value above the threshold will always be on low-power cpus
1534 with less compute capacity.
1536 config SCHED_HMP_PRIO_FILTER_VAL
1537 int "NICE priority threshold"
1539 depends on SCHED_HMP_PRIO_FILTER
1541 config HMP_FAST_CPU_MASK
1542 string "HMP scheduler fast CPU mask"
1543 depends on SCHED_HMP
1545 Leave empty to use device tree information.
1546 Specify the cpuids of the fast CPUs in the system as a list string,
1547 e.g. cpuid 0+1 should be specified as 0-1.
1549 config HMP_SLOW_CPU_MASK
1550 string "HMP scheduler slow CPU mask"
1551 depends on SCHED_HMP
1553 Leave empty to use device tree information.
1554 Specify the cpuids of the slow CPUs in the system as a list string,
1555 e.g. cpuid 0+1 should be specified as 0-1.
1557 config HMP_VARIABLE_SCALE
1558 bool "Allows changing the load tracking scale through sysfs"
1559 depends on SCHED_HMP
1561 When turned on, this option exports the load average period value
1562 for the load tracking patches through sysfs.
1563 The values can be modified to change the rate of load accumulation
1564 used for HMP migration. 'load_avg_period_ms' is the time in ms to
1565 reach a load average of 0.5 for an idle task of 0 load average
1566 ratio which becomes 100% busy.
1567 For example, with load_avg_period_ms = 128 and up_threshold = 512,
1568 a running task with a load of 0 will be migrated to a bigger CPU after
1569 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
1570 up_threshold is 0.5.
1571 This patch has the same behavior as changing the Y of the load
1572 average computation to
1573 (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
1574 but removes intermediate overflows in computation.
1576 config HMP_FREQUENCY_INVARIANT_SCALE
1577 bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
1578 depends on SCHED_HMP && CPU_FREQ
1580 Scales the current load contribution in line with the frequency
1581 of the CPU that the task was executed on.
1582 In this version, we use a simple linear scale derived from the
1583 maximum frequency reported by CPUFreq.
1584 Restricting tracked load to be scaled by the CPU's frequency
1585 represents the consumption of possible compute capacity
1586 (rather than consumption of actual instantaneous capacity as
1587 normal) and allows the HMP migration's simple threshold
1588 migration strategy to interact more predictably with CPUFreq's
1589 asynchronous compute capacity changes.
1591 config SCHED_HMP_LITTLE_PACKING
1592 bool "Small task packing for HMP"
1593 depends on SCHED_HMP
1596 Allows the HMP Scheduler to pack small tasks into CPUs in the
1597 smallest HMP domain.
1598 Controlled by two sysfs files in sys/kernel/hmp.
1599 packing_enable: 1 to enable, 0 to disable packing. Default 1.
1600 packing_limit: runqueue load ratio where a RQ is considered
1601 to be full. Default is NICE_0_LOAD * 9/8.
1606 This option enables support for the ARM system coherency unit
1608 config HAVE_ARM_ARCH_TIMER
1609 bool "Architected timer support"
1611 select ARM_ARCH_TIMER
1613 This option enables support for the ARM architected timer
1618 select CLKSRC_OF if OF
1620 This options enables support for the ARM timer and watchdog unit
1623 bool "Multi-Cluster Power Management"
1624 depends on CPU_V7 && SMP
1626 This option provides the common power management infrastructure
1627 for (multi-)cluster based systems, such as big.LITTLE based
1631 bool "big.LITTLE support (Experimental)"
1632 depends on CPU_V7 && SMP
1635 This option enables support for the big.LITTLE architecture.
1638 bool "big.LITTLE switcher support"
1639 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1641 select ARM_CPU_SUSPEND
1643 The big.LITTLE "switcher" provides the core functionality to
1644 transparently handle transition between a cluster of A15's
1645 and a cluster of A7's in a big.LITTLE system.
1647 config BL_SWITCHER_DUMMY_IF
1648 tristate "Simple big.LITTLE switcher user interface"
1649 depends on BL_SWITCHER && DEBUG_KERNEL
1651 This is a simple and dummy char dev interface to control
1652 the big.LITTLE switcher core code. It is meant for
1653 debugging purposes only.
1656 prompt "Memory split"
1659 Select the desired split between kernel and user memory.
1661 If you are not absolutely sure what you are doing, leave this
1665 bool "3G/1G user/kernel split"
1667 bool "2G/2G user/kernel split"
1669 bool "1G/3G user/kernel split"
1674 default 0x40000000 if VMSPLIT_1G
1675 default 0x80000000 if VMSPLIT_2G
1679 int "Maximum number of CPUs (2-32)"
1685 bool "Support for hot-pluggable CPUs"
1686 depends on SMP && HOTPLUG
1688 Say Y here to experiment with turning CPUs off and on. CPUs
1689 can be controlled through /sys/devices/system/cpu.
1692 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1695 Say Y here if you want Linux to communicate with system firmware
1696 implementing the PSCI specification for CPU-centric power
1697 management operations described in ARM document number ARM DEN
1698 0022A ("Power State Coordination Interface System Software on
1702 bool "Use local timer interrupts"
1706 Enable support for local timers on SMP platforms, rather then the
1707 legacy IPI broadcast method. Local timers allows the system
1708 accounting to be spread across the timer interval, preventing a
1709 "thundering herd" at every timer tick.
1711 # The GPIO number here must be sorted by descending number. In case of
1712 # a multiplatform kernel, we just want the highest value required by the
1713 # selected platforms.
1716 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1717 default 512 if SOC_OMAP5
1718 default 392 if ARCH_U8500
1719 default 352 if ARCH_VT8500
1720 default 288 if ARCH_SUNXI
1721 default 264 if MACH_H4700
1724 Maximum number of GPIOs in the system.
1726 If unsure, leave the default value.
1728 source kernel/Kconfig.preempt
1732 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1733 ARCH_S5PV210 || ARCH_EXYNOS4
1734 default AT91_TIMER_HZ if ARCH_AT91
1735 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1739 def_bool HIGH_RES_TIMERS
1741 config THUMB2_KERNEL
1742 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1743 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1744 default y if CPU_THUMBONLY
1746 select ARM_ASM_UNIFIED
1749 By enabling this option, the kernel will be compiled in
1750 Thumb-2 mode. A compiler/assembler that understand the unified
1751 ARM-Thumb syntax is needed.
1755 config THUMB2_AVOID_R_ARM_THM_JUMP11
1756 bool "Work around buggy Thumb-2 short branch relocations in gas"
1757 depends on THUMB2_KERNEL && MODULES
1760 Various binutils versions can resolve Thumb-2 branches to
1761 locally-defined, preemptible global symbols as short-range "b.n"
1762 branch instructions.
1764 This is a problem, because there's no guarantee the final
1765 destination of the symbol, or any candidate locations for a
1766 trampoline, are within range of the branch. For this reason, the
1767 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1768 relocation in modules at all, and it makes little sense to add
1771 The symptom is that the kernel fails with an "unsupported
1772 relocation" error when loading some modules.
1774 Until fixed tools are available, passing
1775 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1776 code which hits this problem, at the cost of a bit of extra runtime
1777 stack usage in some cases.
1779 The problem is described in more detail at:
1780 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1782 Only Thumb-2 kernels are affected.
1784 Unless you are sure your tools don't have this problem, say Y.
1786 config ARM_ASM_UNIFIED
1790 bool "Use the ARM EABI to compile the kernel"
1792 This option allows for the kernel to be compiled using the latest
1793 ARM ABI (aka EABI). This is only useful if you are using a user
1794 space environment that is also compiled with EABI.
1796 Since there are major incompatibilities between the legacy ABI and
1797 EABI, especially with regard to structure member alignment, this
1798 option also changes the kernel syscall calling convention to
1799 disambiguate both ABIs and allow for backward compatibility support
1800 (selected with CONFIG_OABI_COMPAT).
1802 To use this you need GCC version 4.0.0 or later.
1805 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1806 depends on AEABI && !THUMB2_KERNEL
1809 This option preserves the old syscall interface along with the
1810 new (ARM EABI) one. It also provides a compatibility layer to
1811 intercept syscalls that have structure arguments which layout
1812 in memory differs between the legacy ABI and the new ARM EABI
1813 (only for non "thumb" binaries). This option adds a tiny
1814 overhead to all syscalls and produces a slightly larger kernel.
1815 If you know you'll be using only pure EABI user space then you
1816 can say N here. If this option is not selected and you attempt
1817 to execute a legacy ABI binary then the result will be
1818 UNPREDICTABLE (in fact it can be predicted that it won't work
1819 at all). If in doubt say Y.
1821 config ARCH_HAS_HOLES_MEMORYMODEL
1824 config ARCH_SPARSEMEM_ENABLE
1827 config ARCH_SPARSEMEM_DEFAULT
1828 def_bool ARCH_SPARSEMEM_ENABLE
1830 config ARCH_SELECT_MEMORY_MODEL
1831 def_bool ARCH_SPARSEMEM_ENABLE
1833 config HAVE_ARCH_PFN_VALID
1834 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1837 bool "High Memory Support"
1840 The address space of ARM processors is only 4 Gigabytes large
1841 and it has to accommodate user address space, kernel address
1842 space as well as some memory mapped IO. That means that, if you
1843 have a large amount of physical memory and/or IO, not all of the
1844 memory can be "permanently mapped" by the kernel. The physical
1845 memory that is not permanently mapped is called "high memory".
1847 Depending on the selected kernel/user memory split, minimum
1848 vmalloc space and actual amount of RAM, you may not need this
1849 option which should result in a slightly faster kernel.
1854 bool "Allocate 2nd-level pagetables from highmem"
1857 config HW_PERF_EVENTS
1858 bool "Enable hardware performance counter support for perf events"
1859 depends on PERF_EVENTS
1862 Enable hardware performance counter support for perf events. If
1863 disabled, perf events will use software events only.
1865 config SYS_SUPPORTS_HUGETLBFS
1869 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1875 config FORCE_MAX_ZONEORDER
1876 int "Maximum zone order" if ARCH_SHMOBILE
1877 range 11 64 if ARCH_SHMOBILE
1878 default "12" if SOC_AM33XX
1879 default "9" if SA1111
1882 The kernel memory allocator divides physically contiguous memory
1883 blocks into "zones", where each zone is a power of two number of
1884 pages. This option selects the largest power of two that the kernel
1885 keeps in the memory allocator. If you need to allocate very large
1886 blocks of physically contiguous memory, then you may need to
1887 increase this value.
1889 This config option is actually maximum order plus one. For example,
1890 a value of 11 means that the largest free memory block is 2^10 pages.
1892 config ALIGNMENT_TRAP
1894 depends on CPU_CP15_MMU
1895 default y if !ARCH_EBSA110
1896 select HAVE_PROC_CPU if PROC_FS
1898 ARM processors cannot fetch/store information which is not
1899 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1900 address divisible by 4. On 32-bit ARM processors, these non-aligned
1901 fetch/store instructions will be emulated in software if you say
1902 here, which has a severe performance impact. This is necessary for
1903 correct operation of some network protocols. With an IP-only
1904 configuration it is safe to say N, otherwise say Y.
1906 config UACCESS_WITH_MEMCPY
1907 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1909 default y if CPU_FEROCEON
1911 Implement faster copy_to_user and clear_user methods for CPU
1912 cores where a 8-word STM instruction give significantly higher
1913 memory write throughput than a sequence of individual 32bit stores.
1915 A possible side effect is a slight increase in scheduling latency
1916 between threads sharing the same address space if they invoke
1917 such copy operations with large buffers.
1919 However, if the CPU data cache is using a write-allocate mode,
1920 this option is unlikely to provide any performance gain.
1924 prompt "Enable seccomp to safely compute untrusted bytecode"
1926 This kernel feature is useful for number crunching applications
1927 that may need to compute untrusted bytecode during their
1928 execution. By using pipes or other transports made available to
1929 the process as file descriptors supporting the read/write
1930 syscalls, it's possible to isolate those applications in
1931 their own address space using seccomp. Once seccomp is
1932 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1933 and the task is only allowed to execute a few safe syscalls
1934 defined by each seccomp mode.
1936 config CC_STACKPROTECTOR
1937 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1939 This option turns on the -fstack-protector GCC feature. This
1940 feature puts, at the beginning of functions, a canary value on
1941 the stack just before the return address, and validates
1942 the value just before actually returning. Stack based buffer
1943 overflows (that need to overwrite this return address) now also
1944 overwrite the canary, which gets detected and the attack is then
1945 neutralized via a kernel panic.
1946 This feature requires gcc version 4.2 or above.
1953 bool "Xen guest support on ARM (EXPERIMENTAL)"
1954 depends on ARM && AEABI && OF
1955 depends on CPU_V7 && !CPU_V6
1956 depends on !GENERIC_ATOMIC64
1959 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1966 bool "Flattened Device Tree support"
1969 select OF_EARLY_FLATTREE
1971 Include support for flattened device tree machine descriptions.
1974 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1977 This is the traditional way of passing data to the kernel at boot
1978 time. If you are solely relying on the flattened device tree (or
1979 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1980 to remove ATAGS support from your kernel binary. If unsure,
1983 config DEPRECATED_PARAM_STRUCT
1984 bool "Provide old way to pass kernel parameters"
1987 This was deprecated in 2001 and announced to live on for 5 years.
1988 Some old boot loaders still use this way.
1990 # Compressed boot loader in ROM. Yes, we really want to ask about
1991 # TEXT and BSS so we preserve their values in the config files.
1992 config ZBOOT_ROM_TEXT
1993 hex "Compressed ROM boot loader base address"
1996 The physical address at which the ROM-able zImage is to be
1997 placed in the target. Platforms which normally make use of
1998 ROM-able zImage formats normally set this to a suitable
1999 value in their defconfig file.
2001 If ZBOOT_ROM is not enabled, this has no effect.
2003 config ZBOOT_ROM_BSS
2004 hex "Compressed ROM boot loader BSS address"
2007 The base address of an area of read/write memory in the target
2008 for the ROM-able zImage which must be available while the
2009 decompressor is running. It must be large enough to hold the
2010 entire decompressed kernel plus an additional 128 KiB.
2011 Platforms which normally make use of ROM-able zImage formats
2012 normally set this to a suitable value in their defconfig file.
2014 If ZBOOT_ROM is not enabled, this has no effect.
2017 bool "Compressed boot loader in ROM/flash"
2018 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2020 Say Y here if you intend to execute your compressed kernel image
2021 (zImage) directly from ROM or flash. If unsure, say N.
2024 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2025 depends on ZBOOT_ROM && ARCH_SH7372
2026 default ZBOOT_ROM_NONE
2028 Include experimental SD/MMC loading code in the ROM-able zImage.
2029 With this enabled it is possible to write the ROM-able zImage
2030 kernel image to an MMC or SD card and boot the kernel straight
2031 from the reset vector. At reset the processor Mask ROM will load
2032 the first part of the ROM-able zImage which in turn loads the
2033 rest the kernel image to RAM.
2035 config ZBOOT_ROM_NONE
2036 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2038 Do not load image from SD or MMC
2040 config ZBOOT_ROM_MMCIF
2041 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2043 Load image from MMCIF hardware block.
2045 config ZBOOT_ROM_SH_MOBILE_SDHI
2046 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2048 Load image from SDHI hardware block
2052 config ARM_APPENDED_DTB
2053 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2054 depends on OF && !ZBOOT_ROM
2056 With this option, the boot code will look for a device tree binary
2057 (DTB) appended to zImage
2058 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2060 This is meant as a backward compatibility convenience for those
2061 systems with a bootloader that can't be upgraded to accommodate
2062 the documented boot protocol using a device tree.
2064 Beware that there is very little in terms of protection against
2065 this option being confused by leftover garbage in memory that might
2066 look like a DTB header after a reboot if no actual DTB is appended
2067 to zImage. Do not leave this option active in a production kernel
2068 if you don't intend to always append a DTB. Proper passing of the
2069 location into r2 of a bootloader provided DTB is always preferable
2072 config ARM_ATAG_DTB_COMPAT
2073 bool "Supplement the appended DTB with traditional ATAG information"
2074 depends on ARM_APPENDED_DTB
2076 Some old bootloaders can't be updated to a DTB capable one, yet
2077 they provide ATAGs with memory configuration, the ramdisk address,
2078 the kernel cmdline string, etc. Such information is dynamically
2079 provided by the bootloader and can't always be stored in a static
2080 DTB. To allow a device tree enabled kernel to be used with such
2081 bootloaders, this option allows zImage to extract the information
2082 from the ATAG list and store it at run time into the appended DTB.
2085 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2086 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2088 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2089 bool "Use bootloader kernel arguments if available"
2091 Uses the command-line options passed by the boot loader instead of
2092 the device tree bootargs property. If the boot loader doesn't provide
2093 any, the device tree bootargs property will be used.
2095 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2096 bool "Extend with bootloader kernel arguments"
2098 The command-line arguments provided by the boot loader will be
2099 appended to the the device tree bootargs property.
2104 string "Default kernel command string"
2107 On some architectures (EBSA110 and CATS), there is currently no way
2108 for the boot loader to pass arguments to the kernel. For these
2109 architectures, you should supply some command-line options at build
2110 time by entering them here. As a minimum, you should specify the
2111 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2114 prompt "Kernel command line type" if CMDLINE != ""
2115 default CMDLINE_FROM_BOOTLOADER
2118 config CMDLINE_FROM_BOOTLOADER
2119 bool "Use bootloader kernel arguments if available"
2121 Uses the command-line options passed by the boot loader. If
2122 the boot loader doesn't provide any, the default kernel command
2123 string provided in CMDLINE will be used.
2125 config CMDLINE_EXTEND
2126 bool "Extend bootloader kernel arguments"
2128 The command-line arguments provided by the boot loader will be
2129 appended to the default kernel command string.
2131 config CMDLINE_FORCE
2132 bool "Always use the default kernel command string"
2134 Always use the default kernel command string, even if the boot
2135 loader passes other arguments to the kernel.
2136 This is useful if you cannot or don't want to change the
2137 command-line options your boot loader passes to the kernel.
2141 bool "Kernel Execute-In-Place from ROM"
2142 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2144 Execute-In-Place allows the kernel to run from non-volatile storage
2145 directly addressable by the CPU, such as NOR flash. This saves RAM
2146 space since the text section of the kernel is not loaded from flash
2147 to RAM. Read-write sections, such as the data section and stack,
2148 are still copied to RAM. The XIP kernel is not compressed since
2149 it has to run directly from flash, so it will take more space to
2150 store it. The flash address used to link the kernel object files,
2151 and for storing it, is configuration dependent. Therefore, if you
2152 say Y here, you must know the proper physical address where to
2153 store the kernel image depending on your own flash memory usage.
2155 Also note that the make target becomes "make xipImage" rather than
2156 "make zImage" or "make Image". The final kernel binary to put in
2157 ROM memory will be arch/arm/boot/xipImage.
2161 config XIP_PHYS_ADDR
2162 hex "XIP Kernel Physical Location"
2163 depends on XIP_KERNEL
2164 default "0x00080000"
2166 This is the physical address in your flash memory the kernel will
2167 be linked for and stored to. This address is dependent on your
2171 bool "Kexec system call (EXPERIMENTAL)"
2172 depends on (!SMP || PM_SLEEP_SMP)
2174 kexec is a system call that implements the ability to shutdown your
2175 current kernel, and to start another kernel. It is like a reboot
2176 but it is independent of the system firmware. And like a reboot
2177 you can start any kernel with it, not just Linux.
2179 It is an ongoing process to be certain the hardware in a machine
2180 is properly shutdown, so do not be surprised if this code does not
2181 initially work for you. It may help to enable device hotplugging
2185 bool "Export atags in procfs"
2186 depends on ATAGS && KEXEC
2189 Should the atags used to boot the kernel be exported in an "atags"
2190 file in procfs. Useful with kexec.
2193 bool "Build kdump crash kernel (EXPERIMENTAL)"
2195 Generate crash dump after being started by kexec. This should
2196 be normally only set in special crash dump kernels which are
2197 loaded in the main kernel with kexec-tools into a specially
2198 reserved region and then later executed after a crash by
2199 kdump/kexec. The crash dump kernel must be compiled to a
2200 memory address not used by the main kernel
2202 For more details see Documentation/kdump/kdump.txt
2204 config AUTO_ZRELADDR
2205 bool "Auto calculation of the decompressed kernel image address"
2206 depends on !ZBOOT_ROM && !ARCH_U300
2208 ZRELADDR is the physical address where the decompressed kernel
2209 image will be placed. If AUTO_ZRELADDR is selected, the address
2210 will be determined at run-time by masking the current IP with
2211 0xf8000000. This assumes the zImage being placed in the first 128MB
2212 from start of memory.
2216 menu "CPU Power Management"
2219 source "drivers/cpufreq/Kconfig"
2224 Internal configuration node for common cpufreq on Samsung SoC
2226 config CPU_FREQ_S3C24XX
2227 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2228 depends on ARCH_S3C24XX && CPU_FREQ
2231 This enables the CPUfreq driver for the Samsung S3C24XX family
2234 For details, take a look at <file:Documentation/cpu-freq>.
2238 config CPU_FREQ_S3C24XX_PLL
2239 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2240 depends on CPU_FREQ_S3C24XX
2242 Compile in support for changing the PLL frequency from the
2243 S3C24XX series CPUfreq driver. The PLL takes time to settle
2244 after a frequency change, so by default it is not enabled.
2246 This also means that the PLL tables for the selected CPU(s) will
2247 be built which may increase the size of the kernel image.
2249 config CPU_FREQ_S3C24XX_DEBUG
2250 bool "Debug CPUfreq Samsung driver core"
2251 depends on CPU_FREQ_S3C24XX
2253 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2255 config CPU_FREQ_S3C24XX_IODEBUG
2256 bool "Debug CPUfreq Samsung driver IO timing"
2257 depends on CPU_FREQ_S3C24XX
2259 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2261 config CPU_FREQ_S3C24XX_DEBUGFS
2262 bool "Export debugfs for CPUFreq"
2263 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2265 Export status information via debugfs.
2269 source "drivers/cpuidle/Kconfig"
2273 menu "Floating point emulation"
2275 comment "At least one emulation must be selected"
2278 bool "NWFPE math emulation"
2279 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2281 Say Y to include the NWFPE floating point emulator in the kernel.
2282 This is necessary to run most binaries. Linux does not currently
2283 support floating point hardware so you need to say Y here even if
2284 your machine has an FPA or floating point co-processor podule.
2286 You may say N here if you are going to load the Acorn FPEmulator
2287 early in the bootup.
2290 bool "Support extended precision"
2291 depends on FPE_NWFPE
2293 Say Y to include 80-bit support in the kernel floating-point
2294 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2295 Note that gcc does not generate 80-bit operations by default,
2296 so in most cases this option only enlarges the size of the
2297 floating point emulator without any good reason.
2299 You almost surely want to say N here.
2302 bool "FastFPE math emulation (EXPERIMENTAL)"
2303 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2305 Say Y here to include the FAST floating point emulator in the kernel.
2306 This is an experimental much faster emulator which now also has full
2307 precision for the mantissa. It does not support any exceptions.
2308 It is very simple, and approximately 3-6 times faster than NWFPE.
2310 It should be sufficient for most programs. It may be not suitable
2311 for scientific calculations, but you have to check this for yourself.
2312 If you do not feel you need a faster FP emulation you should better
2316 bool "VFP-format floating point maths"
2317 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2319 Say Y to include VFP support code in the kernel. This is needed
2320 if your hardware includes a VFP unit.
2322 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2323 release notes and additional status information.
2325 Say N if your target does not have VFP hardware.
2333 bool "Advanced SIMD (NEON) Extension support"
2334 depends on VFPv3 && CPU_V7
2336 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2341 menu "Userspace binary formats"
2343 source "fs/Kconfig.binfmt"
2346 tristate "RISC OS personality"
2349 Say Y here to include the kernel code necessary if you want to run
2350 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2351 experimental; if this sounds frightening, say N and sleep in peace.
2352 You can also say M here to compile this support as a module (which
2353 will be called arthur).
2357 menu "Power management options"
2359 source "kernel/power/Kconfig"
2361 config ARCH_SUSPEND_POSSIBLE
2362 depends on !ARCH_S5PC100
2363 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2364 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2367 config ARM_CPU_SUSPEND
2372 source "net/Kconfig"
2374 source "drivers/Kconfig"
2378 source "arch/arm/Kconfig.debug"
2380 source "security/Kconfig"
2382 source "crypto/Kconfig"
2384 source "lib/Kconfig"
2386 source "arch/arm/kvm/Kconfig"