Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt

   1 Rockchip RK3288 LVDS interface
   2 ================================
   3
   4 Required properties:
   5 - compatible: matching the soc type, one of
   6         - "rockchip,rk3288-lvds";
   7         - "rockchip,rk3366-lvds";
   8         - "rockchip,rk3368-lvds";
   9
  10 - reg: physical base address of the controller and length
  11         of memory mapped region.
  12 - reg-names: the name to indicate register. example:
  13         - "mipi_lvds_phy": lvds phy register, this's included in the MIPI phy module
  14         - "mipi_lvds_ctl": lvds control register, this's included in the MIPI
  15                 controller module
  16 - clocks: must include clock specifiers corresponding to entries in the
  17         clock-names property.
  18 - clock-names: must contain "pclk_lvds"
  19
  20 - avdd1v0-supply: regulator phandle for 1.0V analog power
  21 - avdd1v8-supply: regulator phandle for 1.8V analog power
  22 - avdd3v3-supply: regulator phandle for 3.3V analog power
  23
  24 - rockchip,grf: phandle to the general register files syscon
  25
  26 - rockchip,data-mapping: should be "vesa" or "jeida",
  27         This describes how the color bits are laid out in the
  28         serialized LVDS signal.
  29 - rockchip,data-width : should be <18> or <24>;
  30 - rockchip,output: should be "rgb", "lvds" or "duallvds",
  31         This describes the output face.
  32
  33 Optional properties
  34 - pinctrl-names: must contain a "default" entry.
  35 - pinctrl-0: pin control group to be used for this controller.
  36 - pinctrl-1: pin control group to be used for gpio.
  37
  38 Required nodes:
  39
  40 The lvds has two video ports as described by
  41         Documentation/devicetree/bindings/media/video-interfaces.txt.
  42 Their connections are modeled using the OF graph bindings specified in
  43         Documentation/devicetree/bindings/graph.txt.
  44
  45 - video port 0 for the VOP inputs
  46 - video port 1 for either a panel or subsequent encoder
  47
  48 Example:
  49
  50 For Rockchip RK3288:
  51
  52         lvds: lvds@ff96c000 {
  53                 compatible = "rockchip,rk3288-lvds";
  54                 rockchip,grf = <&grf>;
  55                 reg = <0xff96c000 0x4000>;
  56                 clocks = <&cru PCLK_LVDS_PHY>;
  57                 clock-names = "pclk_lvds";
  58                 avdd1v0-supply = <&vdd10_lcd>;
  59                 avdd1v8-supply = <&vcc18_lcd>;
  60                 avdd3v3-supply = <&vcca_33>;
  61                 rockchip,data-mapping = "jeida";
  62                 rockchip,data-width = <24>;
  63                 rockchip,output = "rgb";
  64                 ports {
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67
  68                         lvds_in: port@0 {
  69                                 reg = <0>;
  70
  71                                 lvds_in_vopb: endpoint@0 {
  72                                         reg = <0>;
  73                                         remote-endpoint = <&vopb_out_lvds>;
  74                                 };
  75                                 lvds_in_vopl: endpoint@1 {
  76                                         reg = <1>;
  77                                         remote-endpoint = <&vopl_out_lvds>;
  78                                 };
  79                         };
  80
  81                         lvds_out: port@1 {
  82                                 reg = <1>;
  83
  84                                 lvds_out_panel: endpoint {
  85                                         remote-endpoint = <&panel_in>;
  86                                 };
  87                         };
  88                 };
  89         };
  90
  91 For Rockchip RK3368:
  92
  93         lvds: lvds@ff968000 {
  94                 compatible = "rockchip,rk3368-lvds";
  95                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
  96                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
  97                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
  98                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
  99                 power-domains = <&power RK3368_PD_VIO>;
 100                 rockchip,grf = <&grf>;
 101                 pinctrl-names = "lcdc", "gpio";
 102                 pinctrl-0 = <&lcdc_lcdc>;
 103                 pinctrl-1 = <&lcdc_gpio>;
 104
 105                 ports {
 106
 107                 ...
 108
 109                 };
 110         };