Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

   1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
   2 ================================
   3
   4 Required properties:
   5 - #address-cells: Should be <1>.
   6 - #size-cells: Should be <0>.
   7 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
   8   or "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
   9   or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
  10 - reg: Represent the physical address range of the controller.
  11 - interrupts: Represent the controller's interrupt to the CPU(s).
  12 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as
  13   described in [1].
  14 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
  15 - ports: contain a port node with endpoint definitions as defined in [2].
  16   For vopb,set the reg = <0> and set the reg = <1> for vopl.
  17
  18 Optional properties
  19 - clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
  20   "phy_cfg".phandle to the mipi dsi phy reference clock, name should be 'ref'.
  21 - phys: phandle to third party MIPI PHY node
  22 - phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
  23   attribute, provides phandle to MIPI PHY node
  24
  25 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  26 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
  27
  28 Example:
  29
  30 For Rockchip RK3288:
  31
  32         mipi_dsi: mipi@ff960000 {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  36                 reg = <0xff960000 0x4000>;
  37                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  38                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
  39                          <&cru SCLK_DPHY_TX0_CFG>;
  40                 clock-names = "ref", "pclk", "phy_cfg";
  41                 rockchip,grf = <&grf>;
  42                 status = "okay";
  43
  44                 ports {
  45                         #address-cells = <1>;
  46                         #size-cells = <0>;
  47                         reg = <1>;
  48
  49                         mipi_in: port {
  50                                 #address-cells = <1>;
  51                                 #size-cells = <0>;
  52                                 mipi_in_vopb: endpoint@0 {
  53                                         reg = <0>;
  54                                         remote-endpoint = <&vopb_out_mipi>;
  55                                 };
  56                                 mipi_in_vopl: endpoint@1 {
  57                                         reg = <1>;
  58                                         remote-endpoint = <&vopl_out_mipi>;
  59                                 };
  60                         };
  61                 };
  62
  63                 panel {
  64                         compatible ="boe,tv080wum-nl0";
  65                         reg = <0>;
  66
  67                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  68                         pinctrl-names = "default";
  69                         pinctrl-0 = <&lcd_en>;
  70                         backlight = <&backlight>;
  71                         status = "okay";
  72                 };
  73         };
  74
  75 For Rockchip RK3368:
  76
  77 mipi_dsi_host: mipi-dsi-host@ff960000 {
  78         compatible = "rockchip,rk3368-mipi-dsi";
  79         phys = <&mipi_dphy>;
  80         phy-names = "mipi_dphy";
  81         ...
  82
  83         ports@1 {
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86                 reg = <1>;
  87
  88                 mipi_in: port {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91
  92                         mipi_in_vop: endpoint@0 {
  93                                 reg = <0>;
  94                                 remote-endpoint = <&vop_out_mipi>;
  95                         };
  96                 };
  97         };
  98
  99         dsi_panel: panel@0 {
 100                 compatible = "simple-panel-dsi";
 101                 reg = <0>;
 102                 dsi,lanes = <4>;
 103                 ...
 104         };
 105 };