Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

   1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
   2 ================================
   3
   4 Required properties:
   5 - #address-cells: Should be <1>.
   6 - #size-cells: Should be <0>.
   7 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
   8   or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
   9 - reg: Represent the physical address range of the controller.
  10 - interrupts: Represent the controller's interrupt to the CPU(s).
  11 - clocks, clock-names: Phandles to the controller's pll reference
  12   clock(ref) and APB clock(pclk) as described in [1].
  13 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
  14 - ports: contain a port node with endpoint definitions as defined in [2].
  15   For vopb,set the reg = <0> and set the reg = <1> for vopl.
  16
  17 Optional properties
  18 - clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
  19   "phy_cfg".
  20
  21 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  22 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
  23
  24 Example:
  25         mipi_dsi: mipi@ff960000 {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  29                 reg = <0xff960000 0x4000>;
  30                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  31                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
  32                          <&cru SCLK_DPHY_TX0_CFG>;
  33                 clock-names = "ref", "pclk", "phy_cfg";
  34                 rockchip,grf = <&grf>;
  35                 status = "okay";
  36
  37                 ports {
  38                         #address-cells = <1>;
  39                         #size-cells = <0>;
  40                         reg = <1>;
  41
  42                         mipi_in: port {
  43                                 #address-cells = <1>;
  44                                 #size-cells = <0>;
  45                                 mipi_in_vopb: endpoint@0 {
  46                                         reg = <0>;
  47                                         remote-endpoint = <&vopb_out_mipi>;
  48                                 };
  49                                 mipi_in_vopl: endpoint@1 {
  50                                         reg = <1>;
  51                                         remote-endpoint = <&vopl_out_mipi>;
  52                                 };
  53                         };
  54                 };
  55
  56                 panel {
  57                         compatible ="boe,tv080wum-nl0";
  58                         reg = <0>;
  59
  60                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  61                         pinctrl-names = "default";
  62                         pinctrl-0 = <&lcd_en>;
  63                         backlight = <&backlight>;
  64                         status = "okay";
  65                 };
  66         };