Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt

   1 Rockchip RK3288 specific extensions to the Analogix Display Port
   2 ================================
   3
   4 Required properties:
   5 - compatible: "rockchip,rk3288-dp",
   6               "rockchip,rk3368-edp",
   7               "rockchip,rk3399-edp";
   8
   9 - reg: physical base address of the controller and length
  10
  11 - clocks: from common clock binding: handle to dp clock.
  12           of memory mapped region.
  13
  14 - clock-names: from common clock binding:
  15                Required elements: "dp" "pclk"
  16
  17 - resets: Must contain an entry for each entry in reset-names.
  18           See ../reset/reset.txt for details.
  19
  20 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
  21 - pinctrl-0: pin-control mode. should be <&edp_hpd>
  22
  23 - reset-names: Must include the name "dp"
  24
  25 - rockchip,grf: this soc should set GRF regs, so need get grf here.
  26
  27 - ports: there are 2 port nodes with endpoint definitions as defined in
  28   Documentation/devicetree/bindings/media/video-interfaces.txt.
  29     Port 0: contained 2 endpoints, connecting to the output of vop.
  30     Port 1: contained 1 endpoint, connecting to the input of panel.
  31
  32 For the below properties, please refer to Analogix DP binding document:
  33  * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
  34 - phys (required)
  35 - phy-names (required)
  36 - hpd-gpios (optional)
  37 - force-hpd (optional)
  38 -------------------------------------------------------------------------------
  39
  40 Example:
  41         dp-controller: dp@ff970000 {
  42                 compatible = "rockchip,rk3288-dp";
  43                 reg = <0xff970000 0x4000>;
  44                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  45                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
  46                 clock-names = "dp", "pclk";
  47                 phys = <&dp_phy>;
  48                 phy-names = "dp";
  49
  50                 rockchip,grf = <&grf>;
  51                 resets = <&cru 111>;
  52                 reset-names = "dp";
  53
  54                 pinctrl-names = "default";
  55                 pinctrl-0 = <&edp_hpd>;
  56
  57                 status = "disabled";
  58
  59                 ports {
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         edp_in: port@0 {
  63                                 reg = <0>;
  64                                 #address-cells = <1>;
  65                                 #size-cells = <0>;
  66                                 edp_in_vopb: endpoint@0 {
  67                                         reg = <0>;
  68                                         remote-endpoint = <&vopb_out_edp>;
  69                                 };
  70                                 edp_in_vopl: endpoint@1 {
  71                                         reg = <1>;
  72                                         remote-endpoint = <&vopl_out_edp>;
  73                                 };
  74                         };
  75
  76                         edp_out: port@1 {
  77                                 reg = <1>;
  78                                 #address-cells = <1>;
  79                                 #size-cells = <0>;
  80                                 edp_out_panel: endpoint {
  81                                         reg = <0>;
  82                                         remote-endpoint = <&panel_in_edp>
  83                                 };
  84                         };
  85                 };
  86         };
  87
  88         pinctrl {
  89                 edp {
  90                         edp_hpd: edp-hpd {
  91                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
  92                         };
  93                 };
  94         };