Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt

   1 * Rockchip DMC(Dynamic Memory Controller) device
   2
   3 Required properties:
   4 - compatible: Should be one of the following.
   5   - "rockchip,rk3399-dmc" - for RK3399 SoCs.
   6 - devfreq-events: Node to get DDR loading, Refer to
   7                   Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
   8 - interrupts: The interrupt number to the CPU. The interrupt specifier format
   9               depends on the interrupt controller. It should be DCF interrupts,
  10               when DDR dvfs finish, it will happen.
  11 - clocks: Phandles for clock specified in "clock-names" property
  12 - clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon";
  13 - operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
  14                        for details.
  15 - center-supply: DMC supply node.
  16 - status: Marks the node enabled/disabled.
  17
  18 Optional properties:
  19 - ddr_timing:  DDR timing need to pass to arm trust firmware
  20 - upthreshold: The upthreshold to simpleondeamnd policy
  21 - downdifferential: The downdifferential to simpleondeamnd policy
  22
  23 Example:
  24
  25         ddr_timing: ddr_timing {
  26                 compatible = "rockchip,ddr-timing";
  27                 ddr3_speed_bin = <21>;
  28                 pd_idle = <0>;
  29                 sr_idle = <0>;
  30                 sr_mc_gate_idle = <0>;
  31                 srpd_lite_idle  = <0>;
  32                 standby_idle = <0>;
  33                 dram_dll_dis_freq = <300>;
  34                 phy_dll_dis_freq = <125>;
  35
  36                 ddr3_odt_dis_freq = <333>;
  37                 ddr3_drv = <DDR3_DS_40ohm>;
  38                 ddr3_odt = <DDR3_ODT_120ohm>;
  39                 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
  40                 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
  41                 phy_ddr3_odt = <PHY_DRV_ODT_240>;
  42
  43                 lpddr3_odt_dis_freq = <333>;
  44                 lpddr3_drv = <LP3_DS_34ohm>;
  45                 lpddr3_odt = <LP3_ODT_240ohm>;
  46                 phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
  47                 phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
  48                 phy_lpddr3_odt = <PHY_DRV_ODT_240>;
  49
  50                 lpddr4_odt_dis_freq = <333>;
  51                 lpddr4_drv = <LP4_PDDS_60ohm>;
  52                 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
  53                 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
  54                 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
  55                 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
  56                 phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
  57                 phy_lpddr4_odt = <PHY_DRV_ODT_60>;
  58         };
  59
  60         dmc_opp_table: dmc_opp_table {
  61                 compatible = "operating-points-v2";
  62
  63                 opp00 {
  64                         opp-hz = /bits/ 64 <300000000>;
  65                         opp-microvolt = <900000>;
  66                 };
  67                 opp01 {
  68                         opp-hz = /bits/ 64 <666000000>;
  69                         opp-microvolt = <900000>;
  70                 };
  71         };
  72
  73         dmc: dmc {
  74                 compatible = "rockchip,rk3399-dmc";
  75                 devfreq-events = <&dfi>;
  76                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&cru SCLK_DDRCLK>;
  78                 clock-names = "dmc_clk";
  79                 ddr_timing = <&ddr_timing>;
  80                 operating-points-v2 = <&dmc_opp_table>;
  81                 center-supply = <&ppvar_centerlogic>;
  82                 upthreshold = <15>;
  83                 downdifferential = <10>;
  84                 status = "disabled";
  85         };