Added support for new condition code modeling scheme (i.e. physical register dependen...
[oota-llvm.git] / lib / Target /
drwxr-xr-x   ..
drwxr-xr-x - ARM
drwxr-xr-x - Alpha
drwxr-xr-x - CBackend
drwxr-xr-x - CellSPU
drwxr-xr-x - IA64
-rw-r--r-- 3070 MRegisterInfo.cpp
drwxr-xr-x - MSIL
-rw-r--r-- 709 Makefile
drwxr-xr-x - Mips
drwxr-xr-x - PowerPC
-rw-r--r-- 13639 README.txt
drwxr-xr-x - Sparc
-rw-r--r-- 11366 SubtargetFeature.cpp
-rw-r--r-- 17027 Target.td
-rw-r--r-- 4246 TargetAsmInfo.cpp
-rw-r--r-- 3374 TargetCallingConv.td
-rw-r--r-- 22533 TargetData.cpp
-rw-r--r-- 662 TargetFrameInfo.cpp
-rw-r--r-- 3376 TargetInstrInfo.cpp
-rw-r--r-- 942 TargetMachOWriterInfo.cpp
-rw-r--r-- 6300 TargetMachine.cpp
-rw-r--r-- 4236 TargetMachineRegistry.cpp
-rw-r--r-- 3241 TargetSchedule.td
-rw-r--r-- 32773 TargetSelectionDAG.td
-rw-r--r-- 768 TargetSubtarget.cpp
drwxr-xr-x - X86