oota-llvm.git
2013-06-06 Jakub StaszakUse IRBuilder instead of ConstantInt methods.
2013-06-06 Bill WendlingDon't cache the TargetLoweringInfo object inside of...
2013-06-05 Sean SilvaRename operator== parameter to `RHS`.
2013-06-05 Sean SilvaRemove error-prone methods of BinaryRef.
2013-06-05 Sean SilvaAdd writeAsHex(raw_ostream &) method to BinaryRef.
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function
2013-06-05 Sean SilvaRename BinaryRef::isBinary to more descriptive DataIsHe...
2013-06-05 Sean SilvaAdd BinaryRef binary_size() method.
2013-06-05 Sean SilvaComment BinaryRef::Data.
2013-06-05 Bill WendlingAdd space to assert message.
2013-06-05 Sean SilvaAdd writeAsBinary(raw_ostream &) method to BinaryRef.
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Sean Silva[docs] Add link to C++ ABI document.
2013-06-05 Sean Silva[docs] Add link to SysV ABI document.
2013-06-05 Sean Silva[ELF] Add ELFOSABI_GNU.
2013-06-05 Rafael EspindolaDon't hide the first ELF symbol.
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Sean Silvayaml2obj: split out COFF logic into separate file
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection...
2013-06-05 Sean Silvayaml2obj: add -format=<fmt> to choose input YAML interp...
2013-06-05 Jakub StaszakUse IRBuilder instead of ConstantInt methods. It simpli...
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints
2013-06-05 Rafael EspindolaRepresent symbols with a SymbolIndex,SectionIndex pair.
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-05 Arnold SchwaighoferSubtargetEmitter fix
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to...
2013-06-05 Sylvestre LedruThe GNU/HURD is also using the libc. Therefor, endian...
2013-06-05 Andrew TrickFix a tblgen subtargetemitter bug, for future Swift...
2013-06-05 David BlaikiePR15662: Optimized debug info produces out of order...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaDon't print default values for NumberOfAuxSymbols and...
2013-06-05 Rafael EspindolaHandle (at least don't crash on) relocations with no...
2013-06-05 Rafael EspindolaMove BinaryRef to a new include/llvm/Object/YAML.h...
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register"
2013-06-05 Rafael EspindolaHandle relocations that don't point to symbols.
2013-06-04 Sean Silva[docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE(...
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions.
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure...
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-04 Arnold SchwaighoferSubtargetEmitter fix
2013-06-04 Richard SmithFix link.
2013-06-04 Venkatraman... Sparc: No functionality change. Cleanup whitespaces...
2013-06-04 David MajnemerIndVarSimplify: check if loop invariant expansion can...
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla...
2013-06-04 Bob WilsonRemove "-Wl,-seg1addr -Wl,0xE0000000" from link options.
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Vincent LejeuneR600: Add a test for r183108
2013-06-04 Rafael EspindolaSecond part of pr16069
2013-06-04 Hans WennborgTypo: s/caes/cases/ in SimplifyCFG
2013-06-04 Benjamin KramerPreserve const correctness.
2013-06-04 Vladimir MedicTest commit for user vmedic, to verify commit access...
2013-06-04 Alexey Samsonov[llvm-symbolizer] Avoid calling slow getSymbolSize...
2013-06-04 Bill WendlingWe are now in 3.4 land. We don't need the 3.3 releaese...
2013-06-04 Michael GottesmanIEEE-754R 5.7.2 General Operations is* operations ...
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne...
2013-06-04 Aaron BallmanSilencing an MSVC warning about */ being found outside...
2013-06-04 Shuxin YangFix a defect in code-layout pass, improving Benchmarks...
2013-06-03 Nick LewyckyDelete dead safety check.
2013-06-03 David MajnemerSimplifyCFG: Do not transform PHI to select if doing...
2013-06-03 David MajnemerSimplifyCFG: Small cleanup, use ICmpInst::isEquality()
2013-06-03 Rafael EspindolaRemove dead code.
2013-06-03 Rafael EspindolaUpdate RuntimeDyldELF::findOPDEntrySection the new...
2013-06-03 Rafael EspindolaEnable mcjit tests on ppc64 when building with cmake.
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar...
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI...
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul...
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
2013-06-03 Kostya Serebryany[asan] ASan Linux MIPS32 support (llvm part), patch...
2013-06-03 Ahmed BougachaX86: sub_xmm registers are 128 bits wide.
2013-06-03 Alexey SamsonovCorrect handling invalid filename in llvm-symbolizer
2013-06-03 Manuel KlimekIntroduce needsCleanup() for APFloat and APInt.
2013-06-03 Venkatraman... Sparc: Add support for indirect branch and blockaddress...
next