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AMDGPU: Simplify debug printing
2015-09-10 Matt ArsenaultAMDGPU: Simplify debug printing
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2015-09-10 Matt ArsenaultAMDGPU: Use StringRef value
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2015-09-10 Matt ArsenaultAMDGPU/SI: Fix more cases of losing exec operands
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2015-09-10 Matt ArsenaultAMDGPU/SI: Fix creating v_mov_b32s without exec uses
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2015-09-09 Matt ArsenaultAMDGPU: Extract full 64-bit subregister and use subregs
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2015-09-09 Matt ArsenaultAMDGPU: Remove unused multiclass argument
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2015-09-09 Matt ArsenaultAMDGPU: Fix not encoding src2 of VOP3b instructions
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2015-09-09 Matt ArsenaultSelectionDAG: Support Expand of f16 extloads
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2015-09-09 Matt ArsenaultFix typos / grammar
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2015-09-08 Matt ArsenaultAMDGPU/SI: Fix input vcc operand for VOP2b instructions
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2015-09-08 Matt ArsenaultAdd const overload of findRegisterUseOperand
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2015-09-08 Matt ArsenaultAMDGPU: Mark s_barrier as a high latency instruction
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2015-09-08 Matt ArsenaultAMDGPU: Fix s_barrier flags
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2015-09-08 Matt ArsenaultAMDGPU: Handle sub of constant for DS offset folding
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2015-09-01 Matt ArsenaultAMDGPU: Fix adding redundant implicit operands
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2015-08-29 Matt ArsenaultAMDGPU: Add sdst operand to VOP2b instructions
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2015-08-29 Matt ArsenaultAMDGPU: Set mem operands for spill instructions
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2015-08-29 Matt ArsenaultAMDGPU: Fix dropping mem operands when moving to VALU
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2015-08-28 Matt ArsenaultMake MergeConsecutiveStores look at other stores on...
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2015-08-27 Matt ArsenaultAMDGPU/SI: Add test for folding constants into operands
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2015-08-26 Matt ArsenaultAMDGPU: Delete dead code
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2015-08-26 Matt ArsenaultAMDGPU: Don't reprocess instructions when splitting...
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2015-08-26 Matt ArsenaultAMDGPU: Fix not moving users of s_bfe_i64 to VALU
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2015-08-26 Matt ArsenaultAMDGPU: Don't create intermediate SALU instructions
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2015-08-26 Matt ArsenaultAMDGPU/SI: Report SIFixSGPRLiveRanges changed function
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2015-08-26 Matt ArsenaultAMDGPU: Make sure to reserve super registers
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2015-08-26 Matt ArsenaultAMDGPU: Produce error on dynamic_stackalloc
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2015-08-22 Matt ArsenaultAMDGPU: Allow specifying different opcode on VI for...
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2015-08-22 Matt ArsenaultAMDGPU: Improve accuracy of instruction rates for some...
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2015-08-22 Matt ArsenaultAMDGPU: Use DFS to avoid second loop over function
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2015-08-22 Matt ArsenaultAMDGPU: Make sure to run verifier after SIFixSGPRLiveRanges
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2015-08-22 Matt ArsenaultAMDGPU: Improve debug printing in SIFixSGPRLiveRanges
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2015-08-22 Matt ArsenaultAMDGPU: Move CI instructions into CIInstructions.td
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2015-08-21 Matt ArsenaultAMDGPU: Minor cleanups to help with f16 support
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2015-08-15 Matt ArsenaultAMDGPU/SI: Only look at live out SGPR defs
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2015-08-15 Matt ArsenaultLoopStrengthReduce: Try to pass address space to isLegalAddr...
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2015-08-15 Matt ArsenaultAMDGPU/SI: Fix printing useless info with amdhsa
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2015-08-15 Matt ArsenaultAMDGPU/SI: Update LiveVariables
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2015-08-15 Matt ArsenaultAMDGPU/SI: Update LiveIntervals during SIFixSGPRLiveRanges
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2015-08-15 Matt ArsenaultAMDGPU: Remove unnecessary assert
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2015-08-15 Matt ArsenaultAMDGPU/SI: Make comments more precise.
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2015-08-12 Matt ArsenaultAMDGPU: Fix assert on dbg_value instructions
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2015-08-08 Matt ArsenaultRemove unnecessary includes
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2015-08-08 Matt ArsenaultAMDGPU: Implement AMDGPUOperand::print()
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2015-08-08 Matt ArsenaultAMDGPU/SI: Remove VCCReg
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2015-08-08 Matt ArsenaultAMDGPU/SI: Remove source uses of VCCReg
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2015-08-07 Matt ArsenaultAMDGPU: Assume SMRD access for constant address space
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2015-08-05 Matt ArsenaultAMDGPU/SI: Remove EXECReg
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2015-08-05 Matt ArsenaultAMDGPU: Remove SCCReg.
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2015-07-31 Matt ArsenaultAMDGPU: Fix v16i32 to v16i8 truncstore
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2015-07-31 Matt ArsenaultAMDGPU/SI: Set DwarfRegNum
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2015-07-31 Matt ArsenaultTableGen: Support folding casts from bits to int
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2015-07-30 Matt ArsenaultAMDGPU: Set SubRegIndex size and offset
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2015-07-30 Matt ArsenaultAMDGPU: Fix unreachable when emitting binary debug...
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2015-07-30 Matt ArsenaultAdd amdopencl environment to triple
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2015-07-28 Matt ArsenaultAMDGPU: Don't try to use LDS/vector for private if...
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2015-07-28 Matt ArsenaultAMDGPU: Fix crash if called function is a bitcast
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2015-07-28 Matt ArsenaultAMDGPU: Fix return type of getImplicitParameterOffset.
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2015-07-27 Matt ArsenaultFix assert when inlining a constantexpr addrspacecast
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2015-07-21 Matt ArsenaultAMDGPU: Set isMoveImm on s_movk_i32
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2015-07-17 Matt ArsenaultOnly do fmul (fadd x, x), c combine if the fadd only...
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2015-07-14 Matt ArsenaultAMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
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2015-07-14 Matt ArsenaultAMDGPU/SI: Fix read2 merging into a super register.
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2015-07-13 Matt ArsenaultAMDGPU: Minor cleanups to always inline pass
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2015-07-10 Matt ArsenaultAMDGPU: Fix chains for memory ops dependent on argument...
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2015-07-10 Matt ArsenaultAMDGPU: Use requested chain when lowering arguments
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2015-07-10 Matt ArsenaultDAGCombiner: Assume invariant load cannot alias a store
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2015-07-09 Matt ArsenaultAMDGPU/R600: Return correct chain when lowering loads
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2015-07-06 Matt ArsenaultAMDGPU: Run SIInsertWaits as pre-emit pass
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2015-07-06 Matt ArsenaultAMDGPU/SI: Add debugging subtarget feature for DS offsets
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2015-07-03 Matt ArsenaultAMDGPU: Fix indentation of switch
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2015-06-28 Matt ArsenaultAMDGPU/SI: Fix extra space when printing v_div_fmas_*
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2015-06-26 Matt ArsenaultShow invariant loads in MMO dumping
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2015-06-25 Matt ArsenaultDAGCombiner: Use pop_back_val()
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2015-06-25 Matt ArsenaultDAGCombiner: Remove redundant check
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2015-06-23 Matt ArsenaultAMDGPU: Use getAsInteger instead of atoi
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2015-06-19 Matt ArsenaultAMDGPU: Fix filename in comment
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2015-06-19 Matt ArsenaultAMDGPU: Fix some places missed in rename
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2015-06-17 Matt ArsenaultAMDGPU: Change unreachable into reported error
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2015-06-16 Matt ArsenaultRevert "Revert "Fix merges of non-zero vector stores""
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2015-06-11 Matt ArsenaultSLSR: Pass address space to isLegalAddressingMode
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2015-06-11 Matt ArsenaultFix merges of non-zero vector stores
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2015-06-09 Matt ArsenaultImplement computeKnownBits for min/max nodes
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2015-06-09 Matt ArsenaultR600: Switch to using generic min / max nodes.
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2015-06-09 Matt ArsenaultMC: Add target hook to control symbol quoting
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2015-06-07 Matt ArsenaultSeparateConstOffsetFromGEP: Pass address space to isLegalAdd...
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2015-06-07 Matt ArsenaultMake NaryReassociate pass the address space to isLegalAddres...
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2015-06-07 Matt ArsenaultAdd isLegalAddressingMode address space argument to TTI
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2015-06-04 Matt ArsenaultR600/SI: Reimplement isLegalAddressingMode
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2015-06-04 Matt ArsenaultCodeGenPrepare: Provide address space to isLegalAddressingMode
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2015-06-04 Matt ArsenaultPass address space to isLegalAddressingMode in DAGCombiner
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2015-06-04 Matt ArsenaultR600/SI: Fix some cases for load / store of half
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2015-06-03 Matt ArsenaultR600/SI: Fix tests with triples in them
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2015-06-01 Matt ArsenaultR600/SI: Don't hardcode pointer type
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2015-06-01 Matt ArsenaultAdd address space argument to isLegalAddressingMode
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2015-05-26 Matt ArsenaultMake EmitFunctionHeader virtual
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2015-05-26 Matt ArsenaultForgot to add lit.local.cfg for new R600 directory
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2015-05-26 Matt ArsenaultCodeGenPrepare: Don't match addressing modes through...
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2015-05-24 Matt ArsenaultAdd target hook to allow merging stores of nonzero...
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2015-05-07 Matt ArsenaultR600: Fix comment that mentions AMDIL
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C/C++ LLVM-based compilers that forbids OOTA behaviors