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R600/SI: Try to use v_madak_f32
2015-02-21 Matt ArsenaultR600/SI: Try to use v_madak_f32
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2015-02-21 Matt ArsenaultR600/SI: Don't crash when getting immediate operand...
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2015-02-21 Matt ArsenaultR600/SI: Fix mad*k definitions
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2015-02-20 Matt ArsenaultR600/SI: Remove v_sub_f64 pseudo
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2015-02-20 Matt ArsenaultR600: Use new fmad node.
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2015-02-20 Matt ArsenaultAdd generic fmad DAG node.
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2015-02-18 Matt ArsenaultR600/SI: Rename dst encoding field to be consistent...
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2015-02-18 Matt ArsenaultR600/SI: Consistently capitalize encoding field names
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2015-02-18 Matt ArsenaultR600/SI: Set noNamedPositionallyEncodedOperands
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2015-02-18 Matt ArsenaultR600/SI: Fix src1_modifiers for class instructions
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2015-02-18 Matt ArsenaultR600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
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2015-02-18 Matt ArsenaultR600: Fix operand encoding error
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2015-02-18 Matt ArsenaultR600/SI: Fix encoding error from glc bit on VI SMRD...
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2015-02-18 Matt ArsenaultR600/SI: Fix operand encoding for flat instructions
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2015-02-18 Matt ArsenaultR600/SI: Fix error from vdst on no return atomics
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2015-02-18 Matt ArsenaultR600/SI: Add missing offset operand to buffer bothen
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2015-02-18 Matt ArsenaultR600/SI: Add missing soffset operand to global atomics
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2015-02-18 Matt ArsenaultR600/SI: Fix brace identation
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2015-02-14 Matt ArsenaultR600/SI: Implement correct f64 fdiv
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2015-02-14 Matt ArsenaultR600/SI: Use complex operand folding for div_scale
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2015-02-14 Matt ArsenaultR600/SI: Add tests for div_fmas with inline immediate...
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2015-02-14 Matt ArsenaultR600/SI: Fix implicit vcc operand to v_div_fmas_*
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2015-02-14 Matt ArsenaultR600/SI: Fix schedule model for v_div_scale_{f32|f64}
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2015-02-14 Matt ArsenaultR600/SI: Really fix size of VReg_1
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2015-02-14 Matt ArsenaultR600/SI: Rename encoding field to match docs for VOP3b
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2015-02-14 Matt ArsenaultR600/SI: Fix not encoding src2 for v_div_scale_{f32...
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2015-02-14 Matt ArsenaultR600/SI: Fix VOP3b encoding on VI
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2015-02-14 Matt ArsenaultR600/SI: Fix phys reg copies in SIFoldOperands
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2015-02-14 Matt ArsenaultR600/SI: Fix copies from SGPR to VCC
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2015-02-14 Matt ArsenaultR600/SI: Add hack to copy from a VGPR to VCC
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2015-02-14 Matt ArsenaultR600/SI: Fix size of VReg_1
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2015-02-13 Matt ArsenaultR600/SI: Remove handling of fpimm
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2015-02-13 Matt ArsenaultR600/SI: Allow f64 inline immediates in i64 operands
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2015-02-13 Matt ArsenaultR600/SI: Minor test scheduling fixes
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2015-02-13 Matt ArsenaultR600/SI: Remove unnecessary check for fpimm
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2015-02-05 Matt ArsenaultR600/SI: Fix i64 truncate to i1
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2015-02-05 Matt ArsenaultAdd addrspacecast node to tablegen
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2015-02-05 Matt ArsenaultAdd support for double / float to EndianStream
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2015-01-31 Matt ArsenaultFix typo
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2015-01-31 Matt ArsenaultR600/SI: Only select cvt_flr/cvt_rpi with no NaNs.
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2015-01-29 Matt ArsenaultR600/SI: Implement enableAggressiveFMAFusion
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2015-01-29 Matt ArsenaultR600/SI: Add subtarget feature for if f32 fma is fast
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2015-01-29 Matt ArsenaultR600/SI: Fix tonga's basic scheduling model
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2015-01-26 Matt ArsenaultR600: Cleanup or test
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2015-01-21 Matt ArsenaultR600: Add checks for urem/srem by a constant
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2015-01-21 Matt ArsenaultR600: Add missing tests for i64 srem
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2015-01-21 Matt ArsenaultR600/SI: Custom lower fround
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2015-01-18 Matt ArsenaultR600: Remove redundant test
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2015-01-16 Matt ArsenaultR600: Clean up floor tests
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2015-01-15 Matt ArsenaultR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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2015-01-15 Matt ArsenaultR600/SI: Fix trailing comma with modifiers
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2015-01-15 Matt ArsenaultR600/SI: Improve fpext / fptrunc test coverage
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2015-01-14 Matt ArsenaultR600/SI: Remove some redudant load testcases.
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2015-01-14 Matt ArsenaultR600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 Matt ArsenaultImplement new way of expanding extloads.
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2015-01-13 Matt ArsenaultR600: Implement getRecipEstimate
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2015-01-13 Matt ArsenaultR600: Implement getRsqrtEstimate
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2015-01-13 Matt ArsenaultR600: Make cttz / ctlz cheap to speculate
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2015-01-13 Matt ArsenaultCombine fcmp + select to fminnum / fmaxnum if no nans...
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2015-01-12 Matt ArsenaultR600/SI: Remove redundant setting expand on f64 vectors
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2015-01-08 Matt ArsenaultFix fcmp + fabs instcombines when using the intrinsic
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2015-01-06 Matt ArsenaultR600/SI: Add combine for isinfinite pattern
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2015-01-06 Matt ArsenaultAdd isNegative helper to ConstantFPSDNode
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2015-01-06 Matt ArsenaultAdd isInfinity helper to ConstantFPSDNode
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2015-01-06 Matt ArsenaultR600/SI: Pattern match isinf to v_cmp_class instructions
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2015-01-06 Matt ArsenaultR600/SI: Add basic DAG combines for fp_class
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2015-01-06 Matt ArsenaultR600/SI: Add class intrinsic
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2015-01-06 Matt ArsenaultFix using wrong intrinsic in test
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2015-01-06 Matt ArsenaultConvert fcmp with 0.0 from casted integers to icmp
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2014-12-21 Matt ArsenaultEnable (sext x) == C --> x == (trunc C) combine
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2014-12-19 Matt ArsenaultR600: Remove outdated comment
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2014-12-19 Matt ArsenaultR600/SI: Only form min/max with 1 use.
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2014-12-17 Matt ArsenaultR600/SI: Fix f64 inline immediates
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2014-12-16 Matt ArsenaultNVPTX: Remove duplicate of AsmPrinter::lowerConstant
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2014-12-16 Matt ArsenaultMove lowerConstant to AsmPrinter
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2014-12-12 Matt ArsenaultR600: Fix min/max matching problems with unordered...
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2014-12-12 Matt ArsenaultR600/SI: fmin/fmax_legacy are not associative
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2014-12-12 Matt ArsenaultR600/SI: Don't promote f32 select to i32
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2014-12-12 Matt ArsenaultAdd target hook for whether it is profitable to reduce...
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2014-12-11 Matt ArsenaultR600/SI: Handle physical registers in getOpRegClass
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2014-12-11 Matt ArsenaultR600/SI: Don't verify constant bus usage of flag ops
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2014-12-11 Matt ArsenaultTry to include operand counts for mismatches in tablegen.
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2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
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2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
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2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
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2014-12-08 Matt ArsenaultR600/SI: Move continue after checking s_mov_b32.
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2014-12-06 Matt ArsenaultFix typo
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2014-12-04 Matt ArsenaultAllow target to specify prefix for labels
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2014-12-03 Matt ArsenaultFix sphinx error from Statepoints.rst
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2014-12-03 Matt ArsenaultR600/SI: Fix SIFixSGPRCopies for copies to physical...
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2014-12-03 Matt ArsenaultR600/SI: Remove incorrect assertion
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2014-12-03 Matt ArsenaultR600/SI: Remove i1 pseudo VALU ops
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2014-12-03 Matt ArsenaultR600/SI: Fix suspicious indexing
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2014-12-03 Matt ArsenaultR600/SI: Fix running SILowerI1Copies a second time
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2014-12-03 Matt ArsenaultR600/SI: Fix live range error hidden by SIFoldOperands
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2014-12-03 Matt ArsenaultR600/SI: Change mubuf offsets to print as decimal
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2014-12-02 Matt ArsenaultR600: Cleanup some tests and add missing testcases
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2014-12-01 Matt ArsenaultR600/SI: Various instruction format bit test cleanups
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2014-11-28 Matt ArsenaultR600/SI: Fix assertion on sign extend of 3 vectors
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2014-11-26 Matt ArsenaultR600/SI: Use ZeroOrNegativeOneBooleanContent
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C/C++ LLVM-based compilers that forbids OOTA behaviors