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R600: Clean up instruction class definitions
2013-04-30 Vincent LejeuneR600: Clean up instruction class definitions
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2013-04-30 Vincent LejeuneR600: config section now reports use of killgt
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2013-04-23 Vincent LejeuneR600: Use .AMDGPU.config section to emit stacksize
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2013-04-23 Vincent LejeuneR600: Add CF_END
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2013-04-17 Vincent LejeuneR600: Make Export Instruction not duplicable
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2013-04-17 Vincent LejeuneR600: Export is emitted as a CF_NATIVE inst
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2013-04-17 Vincent LejeuneR600: Emit used GPRs count
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2013-04-10 Vincent LejeuneR600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when...
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2013-04-08 Vincent LejeuneR600: Control Flow support for pre EG gen
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2013-04-04 Vincent LejeuneR600: Use a mask for offsets when encoding instructions
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2013-04-04 Vincent LejeuneR600: Fix wrong address when substituting ENDIF
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2013-04-04 Vincent LejeuneR600: Take export into account when computing cf address
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2013-04-03 Vincent LejeuneR600: Fix last ALU of a clause being emitted in a separate...
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2013-04-03 Vincent LejeuneR600: Factorize maximum alu per clause in a single...
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2013-04-03 Vincent LejeuneR600: Simplify data structure and add DEBUG to R600ControlFl...
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2013-04-03 Vincent LejeuneR600: Consider KILLGT as an ALU instruction
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2013-04-01 Vincent LejeuneR600: Add support for native control flow
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2013-04-01 Vincent LejeuneR600/SI: Share code recording ShaderTypeAttribute between...
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2013-04-01 Vincent LejeuneR600: Emit CF_ALU and use true kcache register.
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2013-03-31 Vincent LejeuneR600: Emit native instructions for tex
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2013-03-14 Vincent LejeuneR600: Factorize code handling Const Read Port limitation
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2013-03-13 Vincent LejeuneR600: Remove unused Outputs variable
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2013-03-11 Vincent LejeuneR600: Fix JUMP handling so that MachineInstr verification...
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2013-03-08 Vincent LejeuneR600: Change addresspace in fold-kcache.ll
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2013-03-05 Vincent LejeuneR600: Do not predicate vector op
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2013-03-05 Vincent LejeuneR600: initial scheduler code
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2013-03-05 Vincent LejeuneR600: Remove LowerConstCopyPass and lower CONST_COPY...
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2013-03-05 Vincent LejeuneR600: Turn BUILD_VECTOR into Reg_Sequence
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2013-03-05 Vincent LejeuneR600: CONST_ADDRESS node is not marked as mayLoad anymore
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2013-03-05 Vincent LejeuneR600: Use MUL_IEEE for trig/fdiv intrinsic
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2013-03-05 Vincent LejeuneR600: Add support for indirect addressing of non default...
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2013-02-18 Vincent LejeuneR600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for...
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2013-02-18 Vincent LejeuneR600: Support for TBO
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2013-02-18 Vincent LejeuneR600: Increase number of ArrayBase Reg to 32
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2013-02-14 Vincent LejeuneR600: Do not fold single instruction with more that...
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2013-02-14 Vincent LejeuneR600: Export instructions are no longer terminator
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2013-02-14 Vincent LejeuneR600: Fold zero/one in export instructions
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2013-02-14 Vincent LejeuneR600: Do not fold modifier/litterals in vector inst
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2013-02-10 Vincent LejeuneTest Commit - Remove some trailing whitespace in R600Instruc...
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C/C++ LLVM-based compilers that forbids OOTA behaviors