projects / oota-llvm.git / search
| 2014-07-15 | Jan Vesely | R600: Implement zero undef variants of ctlz/cttz Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-07-10 | Jan Vesely | R600: Implement float to long/ulong Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-07-10 | Jan Vesely | SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-22 | Jan Vesely | R600: Use LowerSDIVREM for i64 node replace Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-22 | Jan Vesely | R600: Implement custom SDIVREM. Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-22 | Jan Vesely | R600: Add udivrem test Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-18 | Jan Vesely | R600: Expand vector fceil Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-18 | Jan Vesely | R600: Implement 64bit SRA Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-18 | Jan Vesely | R600: Implement 64bit SRL Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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| 2014-06-18 | Jan Vesely | R600: Implement 64bit SHL Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> |
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