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Reapply [RuntimeDyldELF] Fold Placeholder into Addend
2015-04-30 Jan VeselyReinstate revisions r234755, r234759, r234760
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2015-04-29 Jan VeselyCodeGen: Default overflow operations to expand so we...
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-04-13 Jan VeselyRevert revisions r234755, r234759, r234760
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2015-04-13 Jan VeselyR600: Add carry and borrow instructions. Use them to...
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-04-13 Jan VeselyLegalizeDAG: Try to use Overflow operations when expanding...
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-04-12 Jan VeselyR600: Make FMIN/MAXNUM legal on all asics
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-04-12 Jan VeselyR600: remove manual BFE optimization
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-03-13 Jan Veselyr600: Clear visited structure before running.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-03-13 Jan Veselyr600: Use deque and simplify loops in AMDGPUCFGStructurizer
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-03-02 Jan VeselySupport: Use const pointers for reads.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-03-02 Jan VeselyR600: Use c++11 style for loop
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-01-22 Jan VeselyR600: Try to use lower types for 64bit division if...
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-01-22 Jan VeselySelectionDAG: Add KnownBits and SignBits computation...
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2015-01-22 Jan VeselyR600: Simplify LowerUDIVREM
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-17 Jan VeselyMips: Only set divrem i64 to custom on 64bit
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-17 Jan VeselyR600: Add EG to FMA test
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-17 Jan VeselySelectionDAG: Add sext_inreg optimizations
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-14 Jan VeselyReapply "R600: Add new intrinsic to read work dimensions"
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-14 Jan VeselyR600: Add new intrinsic to read work dimensions
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-10-14 Jan VeselyR600: FMA is VecALU only instruction
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-09-05 Jan VeselyR600: Fix FROUND
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-09-04 Jan Veselybuild/cmake: Fix CMP0023 warning with libffi
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-08-13 Jan Veselyutils: Fix segfault in flattencfg
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-08-13 Jan VeselyInitialize FlattenCFG pass
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-08-12 Jan VeselyR600: Use optimized 24bit path in udivrem
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-08-12 Jan VeselyR600: Remove unused code.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-08-12 Jan VeselyR600: Use i24 optimized path for SREM
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-07-31 Jan VeselyR600: Modernize work item intrinsics test
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-07-15 Jan VeselyR600: Implement zero undef variants of ctlz/cttz
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-07-10 Jan VeselyR600: Implement float to long/ulong
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-07-10 Jan VeselySelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-22 Jan VeselyR600: Use LowerSDIVREM for i64 node replace
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-22 Jan VeselyR600: Implement custom SDIVREM.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-22 Jan VeselyR600: Add udivrem test
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-18 Jan VeselyR600: Expand vector fceil
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-18 Jan VeselyR600: Implement 64bit SRA
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-18 Jan VeselyR600: Implement 64bit SRL
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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2014-06-18 Jan VeselyR600: Implement 64bit SHL
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
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C/C++ LLVM-based compilers that forbids OOTA behaviors