oota-llvm.git
11 years agoRename the current PPC BCL definition to BCLalways
Hal Finkel [Thu, 4 Apr 2013 22:55:54 +0000 (22:55 +0000)]
Rename the current PPC BCL definition to BCLalways

BCL is normally a conditional branch-and-link instruction, but has
an unconditional form (which is used in the SjLj code, for example).
To make clear that this BCL instruction definition is specifically
the special unconditional form (which does not meaningfully take
a condition-register input), rename it to BCLalways.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC: Improve code generation for mixed-precision reciprocal sqrt
Hal Finkel [Thu, 4 Apr 2013 22:44:12 +0000 (22:44 +0000)]
PPC: Improve code generation for mixed-precision reciprocal sqrt

The DAGCombine logic that recognized a/sqrt(b) and transformed it into
a multiplication by the reciprocal sqrt did not handle cases where the
sqrt and the division were separated by an fpext or fptrunc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Expand br_cc.
Jyotsna Verma [Thu, 4 Apr 2013 21:18:26 +0000 (21:18 +0000)]
Hexagon: Expand br_cc.

It fixes following tests for Hexagon:

CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReassociate: Avoid iterator invalidation.
Benjamin Kramer [Thu, 4 Apr 2013 21:15:42 +0000 (21:15 +0000)]
Reassociate: Avoid iterator invalidation.

OpndPtrs stored pointers into the Opnd vector that became invalid when the
vector grows. Store indices instead. Sadly I only have a large testcase that
only triggers under valgrind, so I didn't include it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178793 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend will
Jyotsna Verma [Thu, 4 Apr 2013 21:05:46 +0000 (21:05 +0000)]
Disable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend will
never produce a byval parameter with size < 8 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178792 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd back parsing of header charactestics.
Rafael Espindola [Thu, 4 Apr 2013 20:30:52 +0000 (20:30 +0000)]
Add back parsing of header charactestics.

It had been dropped during the switch to yaml::IO. Also add a test going
from yaml2obj to llvm-readobj. It can be extended as we add more
fields/formats to yaml2obj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[XCore] Add bru instruction.
Richard Osborne [Thu, 4 Apr 2013 20:05:35 +0000 (20:05 +0000)]
[XCore] Add bru instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[XCore] The RRegs register class is a superset of GRRegs.
Richard Osborne [Thu, 4 Apr 2013 19:57:46 +0000 (19:57 +0000)]
[XCore] The RRegs register class is a superset of GRRegs.

At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMissing word
Eli Bendersky [Thu, 4 Apr 2013 18:29:19 +0000 (18:29 +0000)]
Missing word

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178774 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAvoid high-latency false CPSR dependencies even for tMOVSi.
Jakob Stoklund Olesen [Thu, 4 Apr 2013 18:25:36 +0000 (18:25 +0000)]
Avoid high-latency false CPSR dependencies even for tMOVSi.

The Thumb2SizeReduction pass avoids false CPSR dependencies, except it
still aggressively creates tMOVi8 instructions because they are so
common.

Avoid creating false CPSR dependencies even for tMOVi8 instructions when
the the CPSR flags are known to have high latency. This allows integer
computation to overlap floating point computations.

Also process blocks in a reverse post-order and propagate high-latency
flags to successors.

<rdar://problem/13468102>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFormatting
Eli Bendersky [Thu, 4 Apr 2013 18:03:41 +0000 (18:03 +0000)]
Formatting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178771 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert r178713
Evan Cheng [Thu, 4 Apr 2013 17:40:53 +0000 (17:40 +0000)]
Revert r178713

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178769 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoNew-password-test commit.
Stepan Dyatkovskiy [Thu, 4 Apr 2013 16:11:18 +0000 (16:11 +0000)]
New-password-test commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178765 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Use a mask for offsets when encoding instructions
Vincent Lejeune [Thu, 4 Apr 2013 14:00:09 +0000 (14:00 +0000)]
R600: Use a mask for offsets when encoding instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Fix wrong address when substituting ENDIF
Vincent Lejeune [Thu, 4 Apr 2013 14:00:03 +0000 (14:00 +0000)]
R600: Fix wrong address when substituting ENDIF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Take export into account when computing cf address
Vincent Lejeune [Thu, 4 Apr 2013 13:59:59 +0000 (13:59 +0000)]
R600: Take export into account when computing cf address

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPropagate path to ASan/MSan symbolizer into test environment to produce useful report...
Alexey Samsonov [Thu, 4 Apr 2013 07:41:00 +0000 (07:41 +0000)]
Propagate path to ASan/MSan symbolizer into test environment to produce useful reports on errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178749 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDocument the return value of SmallSet insert.
Nadav Rotem [Thu, 4 Apr 2013 04:54:21 +0000 (04:54 +0000)]
Document the return value of SmallSet insert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178742 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd SPARC v9 support for select on 64-bit compares.
Jakob Stoklund Olesen [Thu, 4 Apr 2013 03:08:00 +0000 (03:08 +0000)]
Add SPARC v9 support for select on 64-bit compares.

This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.

Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoExplicitly add -Wl,--export-all-symbols on mingw/cygwin.
Rafael Espindola [Thu, 4 Apr 2013 01:19:55 +0000 (01:19 +0000)]
Explicitly add -Wl,--export-all-symbols on mingw/cygwin.

Looks like cmake on windows is not expanding ENABLE_EXPORTS to
-Wl,--export-all-symbols on mingw or cygwin, so add this back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178730 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't export symbols in every binary on linux.
Rafael Espindola [Thu, 4 Apr 2013 01:01:32 +0000 (01:01 +0000)]
Don't export symbols in every binary on linux.

On freebsd this makes sure that symbols are exported on the binaries that need
them. The net result is that we should get symbols in the binaries that need
them on every platform.

On linux x86-64 this reduces the size of the bin directory from 262MB to 250MB.

Patch by Stephen Checkoway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178725 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDebug Info: according to DWARF 2, FORM_ref_addr the same size as an address on
Manman Ren [Thu, 4 Apr 2013 00:22:54 +0000 (00:22 +0000)]
Debug Info: according to DWARF 2, FORM_ref_addr the same size as an address on
the target system.

It was hard-coded to 4 bytes before. I can't get llvm to generate a
ref_addr on a reasonably sized testing case.

rdar://problem/13559431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178722 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRefactored out the helper method FindPredecessorAutoreleaseWithSafePath from ObjCARCO...
Michael Gottesman [Wed, 3 Apr 2013 23:39:14 +0000 (23:39 +0000)]
Refactored out the helper method FindPredecessorAutoreleaseWithSafePath from ObjCARCOpt::OptimizeReturns.

Now ObjCARCOpt::OptimizeReturns is easy to read and reason about.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178715 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRefactored out the helper function FindPredecessorRetainWithSafePath from ObjCARCOpt...
Michael Gottesman [Wed, 3 Apr 2013 23:16:05 +0000 (23:16 +0000)]
Refactored out the helper function FindPredecessorRetainWithSafePath from ObjCARCOpt::OptimizeReturns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178714 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake it possible to include llvm-c without including C++ headers. Patch by Filip...
Evan Cheng [Wed, 3 Apr 2013 23:12:39 +0000 (23:12 +0000)]
Make it possible to include llvm-c without including C++ headers. Patch by Filip Pizlo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178713 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSmall cleanups.
Michael Gottesman [Wed, 3 Apr 2013 23:07:45 +0000 (23:07 +0000)]
Small cleanups.

Cleaned up trailing whitespace and added extra slashes in front of a
function level comment so that it follow the convention of having 3
slashes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178712 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRefactored out a part of ObjCARCOpt::OptimizeReturns into its own method HasSafePathT...
Michael Gottesman [Wed, 3 Apr 2013 23:04:28 +0000 (23:04 +0000)]
Refactored out a part of ObjCARCOpt::OptimizeReturns into its own method HasSafePathToPredecessorCall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178710 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemoved an old comment.
Michael Gottesman [Wed, 3 Apr 2013 23:04:24 +0000 (23:04 +0000)]
Removed an old comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178709 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoClean up arc annotations by moving the top/bottom BB annotations into conditional...
Michael Gottesman [Wed, 3 Apr 2013 22:41:59 +0000 (22:41 +0000)]
Clean up arc annotations by moving the top/bottom BB annotations into conditional macros that no-op in Release mode instead of #ifdef sections of the code.

This is to follow the example of the DEBUG macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178705 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoX86 cost model: Vector shifts are expensive in most cases
Arnold Schwaighofer [Wed, 3 Apr 2013 21:46:05 +0000 (21:46 +0000)]
X86 cost model: Vector shifts are expensive in most cases

The default logic does not correctly identify costs of casts because they are
marked as custom on x86.

For some cases, where the shift amount is a scalar we would be able to generate
better code. Unfortunately, when this is the case the value (the splat) will get
hoisted out of the loop, thereby making it invisible to ISel.

radar://13130673
radar://13537826

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178703 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement the "mips endian" for r_info.
Rafael Espindola [Wed, 3 Apr 2013 21:02:51 +0000 (21:02 +0000)]
Implement the "mips endian" for r_info.

Normally r_info is just a 32 of 64 bit number matching the endian of the rest
of the file. Unfortunately, mips 64 bit little endian is special: The top 32
bits are a little endian number and the following 32 are a big endian one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178694 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[XCore] Check disassembly of the st8 instruction.
Richard Osborne [Wed, 3 Apr 2013 20:07:11 +0000 (20:07 +0000)]
[XCore] Check disassembly of the st8 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[XCore] Update disassembler test to improve coverage of the instructions.
Richard Osborne [Wed, 3 Apr 2013 20:07:06 +0000 (20:07 +0000)]
[XCore] Update disassembler test to improve coverage of the instructions.

Previously some instructions were unintentionally covered twice and
others were not covered at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplements low-level object file format specific output for COFF and
Eric Christopher [Wed, 3 Apr 2013 18:31:38 +0000 (18:31 +0000)]
Implements low-level object file format specific output for COFF and
ELF with support for:

- File headers
- Section headers + data
- Relocations
- Symbols
- Unwind data (only COFF/Win64)

The output format follows a few rules:
- Values are almost always output one per line (as elf-dump/coff-dump already do). - Many values are translated to something readable (like enum names), with the raw value in parentheses.
- Hex numbers are output in uppercase, prefixed with "0x".
- Flags are sorted alphabetically.
- Lists and groups are always delimited.

Example output:
---------- snip ----------
Sections [
  Section {
    Index: 1
    Name: .text (5)
    Type: SHT_PROGBITS (0x1)
    Flags [ (0x6)
      SHF_ALLOC (0x2)
      SHF_EXECINSTR (0x4)
    ]
    Address: 0x0
    Offset: 0x40
    Size: 33
    Link: 0
    Info: 0
    AddressAlignment: 16
    EntrySize: 0
    Relocations [
      0x6 R_386_32 .rodata.str1.1 0x0
      0xB R_386_PC32 puts 0x0
      0x12 R_386_32 .rodata.str1.1 0x0
      0x17 R_386_PC32 puts 0x0
    ]
    SectionData (
      0000: 83EC04C7 04240000 0000E8FC FFFFFFC7  |.....$..........|
      0010: 04240600 0000E8FC FFFFFF31 C083C404  |.$.........1....|
      0020: C3                                   |.|
    )
  }
]
---------- snip ----------

Relocations and symbols can be output standalone or together with the section header as displayed in the example.
This feature set supports all tests in test/MC/COFF and test/MC/ELF (and I suspect all additional tests using elf-dump), making elf-dump and coff-dump deprecated.

Patch by Nico Rieck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178679 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't disassemble symbols with an unknown address or size.
Eric Christopher [Wed, 3 Apr 2013 18:31:23 +0000 (18:31 +0000)]
Don't disassemble symbols with an unknown address or size.

Patch by Nico Rieck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178678 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement sectionContainsSymbol for ELF.
Eric Christopher [Wed, 3 Apr 2013 18:31:19 +0000 (18:31 +0000)]
Implement sectionContainsSymbol for ELF.

Patch by Nico Rieck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178677 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoWhen dumping clear the arm/thumb flag for now.
Eric Christopher [Wed, 3 Apr 2013 18:31:12 +0000 (18:31 +0000)]
When dumping clear the arm/thumb flag for now.

Patch by Nico Rieck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178676 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Fix last ALU of a clause being emitted in a separate clause
Vincent Lejeune [Wed, 3 Apr 2013 18:24:47 +0000 (18:24 +0000)]
R600: Fix last ALU of a clause being emitted in a separate clause

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoEnsuring that both bits are set, and not just a combination of one or the other.
Aaron Ballman [Wed, 3 Apr 2013 18:00:22 +0000 (18:00 +0000)]
Ensuring that both bits are set, and not just a combination of one or the other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178674 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleanup PPC reciprocal-estimate functionality
Hal Finkel [Wed, 3 Apr 2013 17:44:56 +0000 (17:44 +0000)]
Cleanup PPC reciprocal-estimate functionality

Incorporating review feedback from Bill Schmidt on r178617. No functionality
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Factorize maximum alu per clause in a single location
Vincent Lejeune [Wed, 3 Apr 2013 16:49:34 +0000 (16:49 +0000)]
R600: Factorize maximum alu per clause in a single location

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTesting for Visual Studio 2010 SP1 or greater before calling the _xgetbv intrinsic...
Aaron Ballman [Wed, 3 Apr 2013 16:28:24 +0000 (16:28 +0000)]
Testing for Visual Studio 2010 SP1 or greater before calling the _xgetbv intrinsic.  This also fixes a minor code formatting issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178666 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer
Vincent Lejeune [Wed, 3 Apr 2013 16:24:09 +0000 (16:24 +0000)]
R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178665 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Consider KILLGT as an ALU instruction
Vincent Lejeune [Wed, 3 Apr 2013 16:24:04 +0000 (16:24 +0000)]
R600: Consider KILLGT as an ALU instruction

Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178664 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMeasure time that IR parsing took as part of the -time-passes measurement.
Eli Bendersky [Wed, 3 Apr 2013 15:33:45 +0000 (15:33 +0000)]
Measure time that IR parsing took as part of the -time-passes measurement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178662 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC: Enable FRES and FRSQRTE on the default PPC64 description
Hal Finkel [Wed, 3 Apr 2013 14:40:18 +0000 (14:40 +0000)]
PPC: Enable FRES and FRSQRTE on the default PPC64 description

I discussed this with Bill Schmidt on IRC, and it was decided that this is a
safe and reasonable default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC: Add a FIXME regarding the non-working fma+fneg Altivec pattern
Hal Finkel [Wed, 3 Apr 2013 14:40:16 +0000 (14:40 +0000)]
PPC: Add a FIXME regarding the non-working fma+fneg Altivec pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove some obsolete PowerPC/README entries
Hal Finkel [Wed, 3 Apr 2013 14:25:55 +0000 (14:25 +0000)]
Remove some obsolete PowerPC/README entries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178657 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMore direct types in PowerPC AltiVec intrinsics.
Ulrich Weigand [Wed, 3 Apr 2013 14:08:13 +0000 (14:08 +0000)]
More direct types in PowerPC AltiVec intrinsics.

This patch follows up on work done by Bill Schmidt in r178277,
and replaces most of the remaining uses of VRRC in ISEL DAG patterns.

The resulting .inc files are identical except for comments, so
no change in code generation is expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix PR15632: No support for ppcf128 floating-point remainder on PowerPC.
Bill Schmidt [Wed, 3 Apr 2013 13:05:44 +0000 (13:05 +0000)]
Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.

For this we need to use a libcall.  Previously LLVM didn't implement
libcall support for frem, so I've added it in the usual
straightforward manner.  A test case from the bug report is included.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: implement ETMv4 trace system registers.
Tim Northover [Wed, 3 Apr 2013 12:31:29 +0000 (12:31 +0000)]
AArch64: implement ETMv4 trace system registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSecond pass at addressing PR15351 by explicitly checking for AVX support
Aaron Ballman [Wed, 3 Apr 2013 12:25:06 +0000 (12:25 +0000)]
Second pass at addressing PR15351 by explicitly checking for AVX support
when getting the host processor information.  It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178636 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTemporarily relax the WIN32 checks in the SRet test to fix the Atom D2700 bot
Timur Iskhodzhanov [Wed, 3 Apr 2013 12:17:15 +0000 (12:17 +0000)]
Temporarily relax the WIN32 checks in the SRet test to fix the Atom D2700 bot

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178635 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix SRet for thiscall in i686-pc-win32
Timur Iskhodzhanov [Wed, 3 Apr 2013 11:27:54 +0000 (11:27 +0000)]
Fix SRet for thiscall in i686-pc-win32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: switch patterns to be type-based rather than RegClass-based
Tim Northover [Wed, 3 Apr 2013 11:19:16 +0000 (11:19 +0000)]
AArch64: switch patterns to be type-based rather than RegClass-based

It's a bit of churn in the blame log, but I think there are real benefits to
the newer system so I'm making the change in one go.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix grammar.
Eric Christopher [Wed, 3 Apr 2013 05:29:58 +0000 (05:29 +0000)]
Fix grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178624 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove ZeroOrMore from the option description. We don't need it here.
Eric Christopher [Wed, 3 Apr 2013 05:26:07 +0000 (05:26 +0000)]
Remove ZeroOrMore from the option description. We don't need it here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178623 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd 64-bit compare + branch for SPARC v9.
Jakob Stoklund Olesen [Wed, 3 Apr 2013 04:41:44 +0000 (04:41 +0000)]
Add 64-bit compare + branch for SPARC v9.

The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.

This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178621 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove some unsupported-feature comments from PPC.td
Hal Finkel [Wed, 3 Apr 2013 04:03:58 +0000 (04:03 +0000)]
Remove some unsupported-feature comments from PPC.td

These refer to the reciprocal estimate support recently committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse PPC reciprocal estimates with Newton iteration in fast-math mode
Hal Finkel [Wed, 3 Apr 2013 04:01:11 +0000 (04:01 +0000)]
Use PPC reciprocal estimates with Newton iteration in fast-math mode

When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.

I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the fde encoding used by mips to match gas.
Rafael Espindola [Wed, 3 Apr 2013 03:13:19 +0000 (03:13 +0000)]
Fix the fde encoding used by mips to match gas.

This finally fixes the encoding. The patch also
* Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking
  the wrong value.
* Merge fde-reloc.s and eh-frame.s into a single test, since the only difference
  was the run lines.
* Don't blindly test the content of the entire .eh_frame section. It makes it
  hard to anyone actually fixing a bug and hitting a difference in a binary
  blob. Instead, use a CHECK for each field and document what is being checked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn...
Aaron Ballman [Wed, 3 Apr 2013 03:11:39 +0000 (03:11 +0000)]
Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn't understand the xgetbv instruction for some reason.  Will revisit when time permits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove an optimization where we were changing an objc_autorelease into an objc_autore...
Michael Gottesman [Wed, 3 Apr 2013 02:57:24 +0000 (02:57 +0000)]
Remove an optimization where we were changing an objc_autorelease into an objc_autoreleaseReturnValue.

The semantics of ARC implies that a pointer passed into an objc_autorelease
must live until some point (potentially down the stack) where an
autorelease pool is popped. On the other hand, an
objc_autoreleaseReturnValue just signifies that the object must live
until the end of the given function at least.

Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in
terms of the semantics of ARC* implying that performing the given
strength reduction without any knowledge of how this relates to
the autorelease pool pop that is further up the stack violates the
semantics of ARC.

*Even though objc_autoreleaseReturnValue if you know that no RV
optimization will occur is more computationally expensive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178612 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImproved comment. No functionality change.
Michael Gottesman [Wed, 3 Apr 2013 01:57:16 +0000 (01:57 +0000)]
Improved comment. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178605 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAttempting to fix the build on older GCC versions.
Aaron Ballman [Wed, 3 Apr 2013 01:39:37 +0000 (01:39 +0000)]
Attempting to fix the build on older GCC versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178604 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove anonymous namespace.
Rafael Espindola [Wed, 3 Apr 2013 01:07:53 +0000 (01:07 +0000)]
Remove anonymous namespace.

Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage":

/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value':
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281:   instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >'
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627:   instantiated from here
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178600 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoThis patch addresses PR15351 by explicitly checking for AVX support
Aaron Ballman [Wed, 3 Apr 2013 00:33:32 +0000 (00:33 +0000)]
This patch addresses PR15351 by explicitly checking for AVX support
when getting the host processor information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178598 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse yaml::IO in yaml2obj.cpp.
Rafael Espindola [Tue, 2 Apr 2013 23:56:40 +0000 (23:56 +0000)]
Use yaml::IO in yaml2obj.cpp.

The generic structs and specializations will be refactored when obj2yaml is
changed to use yaml::IO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178593 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFormatting.
Eric Christopher [Tue, 2 Apr 2013 23:06:40 +0000 (23:06 +0000)]
Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Small update to the implementation of eh.return for Mips.
Akira Hatanaka [Tue, 2 Apr 2013 23:02:07 +0000 (23:02 +0000)]
[mips] Small update to the implementation of eh.return for Mips.

This patch initializes t9 to the handler address, but only if the relocation
model is pic. This handles the case where handler to which eh.return jumps
points to the start of the function.

Patch by Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSupport and test template arguments for unions.
Eric Christopher [Tue, 2 Apr 2013 22:55:56 +0000 (22:55 +0000)]
Support and test template arguments for unions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178586 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReformat arguments.
Eric Christopher [Tue, 2 Apr 2013 22:55:52 +0000 (22:55 +0000)]
Reformat arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178585 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.
Akira Hatanaka [Tue, 2 Apr 2013 22:53:58 +0000 (22:53 +0000)]
[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.

This patch fixes the following two tests which have been failing on
llvm-mips-linux builder since r178403:

LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll
LLVM :: Analysis/Profiling/load-branch-weights-loops.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178584 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agollvm/test/CodeGen/X86: Unmark them out of XFAIL:cygming, in atomic{32|64}.ll and...
NAKAMURA Takumi [Tue, 2 Apr 2013 22:35:08 +0000 (22:35 +0000)]
llvm/test/CodeGen/X86: Unmark them out of XFAIL:cygming, in atomic{32|64}.ll and handle-move.ll, corresponding to r178549.

This reverts r176808, r176798, and r177914.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178583 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow MachineTraceMetrics to be used when the model has no resources.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 22:27:45 +0000 (22:27 +0000)]
Allow MachineTraceMetrics to be used when the model has no resources.

It it still possible to extract information from itineraries, for
example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178582 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix a typo.
Jakub Staszak [Tue, 2 Apr 2013 20:02:36 +0000 (20:02 +0000)]
Fix a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178567 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ms-inline asm] Add support for parsing variables with namespace alias
Chad Rosier [Tue, 2 Apr 2013 20:02:33 +0000 (20:02 +0000)]
[ms-inline asm] Add support for parsing variables with namespace alias
qualifiers.

This patch only adds support for parsing these identifiers in the
X86AsmParser.  The front-end interface isn't capable of looking up
these identifiers at this point in time.  The end result is the
compiler now errors during object file emission, rather than at
parse time.  Test case coming shortly.
Part of rdar://13499009 and PR13340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178566 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd MDBuilder utilities for path-aware TBAA.
Manman Ren [Tue, 2 Apr 2013 19:50:49 +0000 (19:50 +0000)]
Add MDBuilder utilities for path-aware TBAA.

Add utilities to create struct nodes in TBAA type DAG and to create path-aware
tags. The format of struct nodes in TBAA type DAG: a unique name, a list of
fields with field offsets and field types. The format of path-aware tags:
a base type in TBAA type DAG, an access type and an offset relative to the base
type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178564 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix PR15630: Replace faulty stdcx. with stwcx.
Bill Schmidt [Tue, 2 Apr 2013 18:37:08 +0000 (18:37 +0000)]
Fix PR15630:  Replace faulty stdcx. with stwcx.

When doing a partword atomic operation, a lwarx was being paired with
a stdcx. instead of a stwcx. when compiling for a 64-bit target.  The
target has nothing to do with it in this case; we always need a stwcx.

Thanks to Kai Nacke for reporting the problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't attempt MTM heuristics without a scheduling model present.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 18:26:45 +0000 (18:26 +0000)]
Don't attempt MTM heuristics without a scheduling model present.

This should fix the PPC buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178558 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCount processor resources individually in MachineTraceMetrics.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 17:49:51 +0000 (17:49 +0000)]
Count processor resources individually in MachineTraceMetrics.

The new instruction scheduling models provide information about the
number of cycles consumed on each processor resource. This makes it
possible to estimate ILP more accurately than simply counting
instructions / issue width.

The functions getResourceDepth() and getResourceLength() now identify
the limiting processor resource, and return a cycle count based on that.

This gives more precise resource information, particularly in traces
that use one resource a lot more than others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178553 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[fast-isel] Use the correct API to disable FastLowerArguments for Win64.
Chad Rosier [Tue, 2 Apr 2013 16:31:41 +0000 (16:31 +0000)]
[fast-isel] Use the correct API to disable FastLowerArguments for Win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDAGCombiner: Merge store/loads when we have extload/truncstores
Arnold Schwaighofer [Tue, 2 Apr 2013 15:58:51 +0000 (15:58 +0000)]
DAGCombiner: Merge store/loads when we have extload/truncstores

This is helps on architectures where i8,i16 are not legal but we have byte, and
short loads/stores. Allowing us to merge copies like the one below on ARM.

copy(char *a, char *b, int n) {
 do {
   int t0 = a[0];
   int t1 = a[1];
   b[0] = t0;
   b[1] = t1;

radar://13536387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSimplify test cases for Atom preferring call register indirect over
Preston Gurd [Tue, 2 Apr 2013 14:25:06 +0000 (14:25 +0000)]
Simplify test cases for Atom preferring call register indirect over
call memory indirect (32 and 64 bit).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178541 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Fix a few style issues in NVVMReflect
Justin Holewinski [Tue, 2 Apr 2013 12:37:11 +0000 (12:37 +0000)]
[NVPTX] Fix a few style issues in NVVMReflect

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178536 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse a worklist to avoid a sneaky iterator invalidation.
Bill Wendling [Tue, 2 Apr 2013 08:16:45 +0000 (08:16 +0000)]
Use a worklist to avoid a sneaky iterator invalidation.

The iterator could be invalidated when it's recursively deleting a whole bunch
of constant expressions in a constant initializer.

Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was
run on a `.ll' file, it wouldn't crash. This is why the test first pushes the
`.ll' file through `llvm-as' before feeding it to `opt'.

PR15440

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178531 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd 64-bit load and store instructions.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:28 +0000 (04:09 +0000)]
Add 64-bit load and store instructions.

There is only a few new instructions, the rest is handled with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoBasic 64-bit ALU operations.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:23 +0000 (04:09 +0000)]
Basic 64-bit ALU operations.

SPARC v9 extends all ALU instructions to 64 bits, so we simply need to
add patterns to use them for both i32 and i64 values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMaterialize 64-bit immediates.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:17 +0000 (04:09 +0000)]
Materialize 64-bit immediates.

The last resort pattern produces 6 instructions, and there are still
opportunities for materializing some immediates in fewer instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178526 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd 64-bit shift instructions.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:12 +0000 (04:09 +0000)]
Add 64-bit shift instructions.

SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd predicates for distinguishing 32-bit and 64-bit modes.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:06 +0000 (04:09 +0000)]
Add predicates for distinguishing 32-bit and 64-bit modes.

The 'sparc' architecture produces 32-bit code while 'sparcv9' produces
64-bit code.

It is also possible to run 32-bit code using SPARC v9 instructions with:

  llc -march=sparc -mattr=+v9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178524 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd support for 64-bit calling convention.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:09:02 +0000 (04:09 +0000)]
Add support for 64-bit calling convention.

This is far from complete, but it is enough to make it possible to write
test cases using i64 arguments.

Missing features:
- Floating point arguments.
- Receiving arguments on the stack.
- Calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd an I64Regs register class for 64-bit registers.
Jakob Stoklund Olesen [Tue, 2 Apr 2013 04:08:54 +0000 (04:08 +0000)]
Add an I64Regs register class for 64-bit registers.

We are going to use the same registers for 32-bit and 64-bit values, but
in two different register classes. The I64Regs register class has a
larger spill size and alignment.

The addition of an i64 register class confuses TableGen's type
inference, so it is necessary to clarify the type of some immediates and
the G0 register.

In 64-bit mode, pointers are i64 and should use the I64Regs register
class. Implement getPointerRegClass() to dynamically provide the pointer
register class depending on the subtarget. Use ptr_rc and iPTR for
memory operands.

Finally, add the i64 type to the IntRegs register class. This register
class is not used to hold i64 values, I64Regs is for that. The type is
required to appease TableGen's type checking in output patterns like this:

  def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;

SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and
TableGen doesn't know to check the type of register sub-classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix typo in PPCISelLowering
Hal Finkel [Tue, 2 Apr 2013 03:29:51 +0000 (03:29 +0000)]
Fix typo in PPCISelLowering

Thanks to Bill Schmidt for finding this in review of r178480.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoThe divide unit is not pipeline, but it is still buffered.
Andrew Trick [Tue, 2 Apr 2013 01:58:47 +0000 (01:58 +0000)]
The divide unit is not pipeline, but it is still buffered.

Buffered means a later divide may be executed out-of-order while a
prior divide is sitting (buffered) in a reservation station.

You can tell it's not pipelined, because operations that use it
reserve it for more than one cycle:

def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
  let Latency = 25;
  let ResourceCycles = [1, 10];
}

We don't currently distinguish between an unpipeline operation and one
that is split into multiple micro-ops requiring the same unit. Except
that the later may have NumMicroOps > 1 if they also consume
issue/dispatch resources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agounindent the file to follow coding standards, change class doc comment
Chris Lattner [Mon, 1 Apr 2013 23:00:01 +0000 (23:00 +0000)]
unindent the file to follow coding standards, change class doc comment
to be correct.  No functionality or behavior change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178511 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTarget/R600: Fix CMake build to add missing files.
NAKAMURA Takumi [Mon, 1 Apr 2013 22:05:58 +0000 (22:05 +0000)]
Target/R600: Fix CMake build to add missing files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178508 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMips direct object exception handling regression
Jack Carter [Mon, 1 Apr 2013 21:55:15 +0000 (21:55 +0000)]
Mips direct object exception handling regression

Revision 177141 caused a regression in all but
mips64 little endian. That is because none of the
other Mips targets had test cases checking the
contents of the .eh_frame section. This patch fixes
both the llvm code and adds an assembler test case
to include the current 4 flavors.

The test cases unfortunately rely on llvm-objdump. A
preferable method would be to use a pretty printer output
such as what readelf -wf <elf_file> would give.

I also changed the name of the test case to correct a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178506 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Add support for native control flow
Vincent Lejeune [Mon, 1 Apr 2013 21:48:05 +0000 (21:48 +0000)]
R600: Add support for native control flow

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178505 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Share code recording ShaderTypeAttribute between generations
Vincent Lejeune [Mon, 1 Apr 2013 21:47:53 +0000 (21:47 +0000)]
R600/SI: Share code recording ShaderTypeAttribute between generations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178504 91177308-0d34-0410-b5e6-96231b3b80d8