oota-llvm.git
11 years agoRemove testcase. It's failing on some platforms but not others.
Bill Wendling [Tue, 26 Mar 2013 01:10:03 +0000 (01:10 +0000)]
Remove testcase. It's failing on some platforms but not others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177956 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHmm...not failing...odd
Bill Wendling [Tue, 26 Mar 2013 01:08:02 +0000 (01:08 +0000)]
Hmm...not failing...odd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177955 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTemporarily XFAIL this test until Michael can look at it.
Bill Wendling [Tue, 26 Mar 2013 00:46:31 +0000 (00:46 +0000)]
Temporarily XFAIL this test until Michael can look at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177953 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ObjCARC Annotations] Added support for displaying the state of pointers at the botto...
Michael Gottesman [Tue, 26 Mar 2013 00:42:09 +0000 (00:42 +0000)]
[ObjCARC Annotations] Added support for displaying the state of pointers at the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses.

This will allow for verification and analysis of the merge function of
the data flow analyses in the ARC optimizer.

The actual implementation of this feature is by introducing calls to
the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend}
which are only declared. Each such call takes in a pointer to a global
with the same name as the pointer whose provenance is being tracked and
a pointer whose name is one of our Sequence states and points to a
string that contains the same name.

To ensure that the optimizer does not consider these annotations in any
way, I made it so that the annotations are considered to be of IC_None
type.

A test case is included for this commit and the previous
ObjCARCAnnotation commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177952 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC data...
Michael Gottesman [Tue, 26 Mar 2013 00:42:04 +0000 (00:42 +0000)]
[ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC data flow analysis state in the IR via metadata.

Previously the inner works of the data flow analysis in ObjCARCOpts was hard to
get out of the optimizer for analysis of bugs or testing. All of the current ARC
unit tests are based off of testing the effect of the data flow
analysis (i.e. what statements are removed or moved, etc.). This creates
weakness in the current unit testing regimem since we are not actually testing
what effects various instructions have on the modeled pointer state.
Additionally in order to analyze a bug in the optimizer, one would need to track
by hand what the optimizer was actually doing either through use of DEBUG
statements or through the usage of a debugger, both yielding large loses in
developer productivity.

This patch deals with these two issues by providing ARC annotation
metadata that annotates instructions with the state changes that they cause in
various pointers as well as provides metadata to annotate provenance sources.

Specifically, we introduce the following metadata types:

1. llvm.arc.annotation.bottomup.
2. llvm.arc.annotation.topdown.
3. llvm.arc.annotation.provenancesource.

llvm.arc.annotation.{bottomup,topdown}: These annotations describes a state
change in a pointer when we are visiting instructions bottomup/topdown
respectively. The output format for both is the same:

  !1 = metadata !{metadata !"(test,%x)", metadata !"S_Release", metadata !"S_Use"}

The first element is a string tuple with the following format:

  (function,variable name)

The second two elements of the metadata show the previous state of the
pointer (in this case S_Release) and the new state of the pointer (S_Use). We
write the metadata in such a manner to ensure that it is easy for outside tools
to parse. This is important since I am currently working on a tool for taking
this information and pretty printing it besides the IR and that can be used for
LIT style testing via the generation of an index.

llvm.arc.annotation.provenancesource: This metadata is used to annotate
instructions which act as provenance sources, i.e. ones that introduce a
new (from the optimizer's perspective) non-argument pointer to track. This
enables cross-referencing in between provenance sources and the state changes
that occur to them.

This is still a work in progress. Additionally I plan on committing
later today additions to the annotations that annotate at the top/bottom
of basic blocks the state of the various pointers being tracked.

*NOTE* The metadata support is conditionally compiled into libObjCARCOpts only
when we are producing a debug build of llvm/clang and even so are
disabled by default. To enable the annotation metadata, pass in
-enable-objc-arc-annotations to opt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177951 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded documentation to LangRef for the intrinsic llvm.ptr.annotation.* which for...
Michael Gottesman [Tue, 26 Mar 2013 00:34:27 +0000 (00:34 +0000)]
Added documentation to LangRef for the intrinsic llvm.ptr.annotation.* which for some reason was never written.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177950 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevise alignment checking/calculation on 256-bit unaligned memory access
Michael Liao [Mon, 25 Mar 2013 23:50:10 +0000 (23:50 +0000)]
Revise alignment checking/calculation on 256-bit unaligned memory access

- It's still considered aligned when the specified alignment is larger
  than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
  alignment) as the pointer is advanced by 16, a power-of-2 offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoEnhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)
Michael Liao [Mon, 25 Mar 2013 23:47:35 +0000 (23:47 +0000)]
Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)

- Handle the case where the result of 'insert_subvect' is bitcasted
  before 'extract_subvec'. This removes the redundant insertf128/extractf128
  pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd an -mcpu option to a test that is apparently scheduler-sensitive.
Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:43:23 +0000 (23:43 +0000)]
Add an -mcpu option to a test that is apparently scheduler-sensitive.

This should fix the clang-atom-d2700-ubuntu-rel buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177943 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a scheduling model for Intel Sandy Bridge microarchitecture.
Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:37:17 +0000 (23:37 +0000)]
Add a scheduling model for Intel Sandy Bridge microarchitecture.

The model isn't hooked up by this patch because the instruction set
isn't fully annotated yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177942 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoIntroduce a tiny CMake project to gather Subversion revision information and place...
Douglas Gregor [Mon, 25 Mar 2013 23:14:19 +0000 (23:14 +0000)]
Introduce a tiny CMake project to gather Subversion revision information and place it into a header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177938 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove IIC_DEFAULT from X86Schedule.td
Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:12:41 +0000 (23:12 +0000)]
Remove IIC_DEFAULT from X86Schedule.td

All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAnnotate X86InstrCompiler.td with SchedRW lists.
Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:35 +0000 (23:07 +0000)]
Annotate X86InstrCompiler.td with SchedRW lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177936 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAnnotate shifts and rotates with SchedRW lists.
Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:32 +0000 (23:07 +0000)]
Annotate shifts and rotates with SchedRW lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable some unsafe-fp-math DAG-combine transformation after legalization.
Shuxin Yang [Mon, 25 Mar 2013 22:52:29 +0000 (22:52 +0000)]
Disable some unsafe-fp-math DAG-combine transformation after legalization.
For instance, following transformation will be disabled:
    x + x + x => 3.0f * x;

The problem of these transformations is that it introduces a FP constant, which
following Instruction-Selection pass cannot handle.

Reviewed by Nadav, thanks a lot!

rdar://13445387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd an optimizer-side test case for ARC bug <rdar://13195034>, fixed
John McCall [Mon, 25 Mar 2013 22:09:52 +0000 (22:09 +0000)]
Add an optimizer-side test case for ARC bug <rdar://13195034>, fixed
in the frontend with @clang.arc.use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177928 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCouple more sets of tidying.
Eric Christopher [Mon, 25 Mar 2013 21:26:36 +0000 (21:26 +0000)]
Couple more sets of tidying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable profiling tests for Hexagon since it doesn't support JIT.
Jyotsna Verma [Mon, 25 Mar 2013 21:15:11 +0000 (21:15 +0000)]
Disable profiling tests for Hexagon since it doesn't support JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177917 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agollvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.
NAKAMURA Takumi [Mon, 25 Mar 2013 21:07:53 +0000 (21:07 +0000)]
llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.

I know it is incorrect and they'd fail with +Asserts for win32 targets, though.
I'll try to fix them tonight.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177914 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoXFAIL some of the generic CodeGen tests for Hexagon.
Jyotsna Verma [Mon, 25 Mar 2013 21:04:16 +0000 (21:04 +0000)]
XFAIL some of the generic CodeGen tests for Hexagon.

test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon.

Following tests are XFAILed due to multiple return values which Hexagon doesn't support.

test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
test/CodeGen/Generic/select-cc.ll
test/CodeGen/Generic/vector.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoX86DisassemblerDecoder.c: Make this C89-compliant.
NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:49 +0000 (20:55 +0000)]
X86DisassemblerDecoder.c: Make this C89-compliant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177910 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoWhitespace.
NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:43 +0000 (20:55 +0000)]
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177909 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix a bug in fast-math fadd/fsub simplification.
Shuxin Yang [Mon, 25 Mar 2013 20:43:41 +0000 (20:43 +0000)]
Fix a bug in fast-math fadd/fsub simplification.

The problem is that the code mistakenly took for granted that following constructor
is able to create an APFloat from a *SIGNED* integer:

  APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value)

rdar://13486998

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177906 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ELF] dont compute symbolname size in every loop
Shankar Easwaran [Mon, 25 Mar 2013 20:26:47 +0000 (20:26 +0000)]
[ELF] dont compute symbolname size in every loop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177903 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoXFAIL DebugInfo tests for Hexagon.
Jyotsna Verma [Mon, 25 Mar 2013 20:20:34 +0000 (20:20 +0000)]
XFAIL DebugInfo tests for Hexagon.

Hexagon does not support -filetype=obj(direct object generation) flag. Therefore,
the following tests are being XFAILed:

test/DebugInfo/dwarf-public-names.ll
test/DebugInfo/member-pointers.ll
test/DebugInfo/two-cus-from-same-file.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177901 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix comment.
Akira Hatanaka [Mon, 25 Mar 2013 20:11:16 +0000 (20:11 +0000)]
Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177899 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFormatting.
Eric Christopher [Mon, 25 Mar 2013 20:05:35 +0000 (20:05 +0000)]
Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177898 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable Execution Engine tests not supported by Hexagon.
Jyotsna Verma [Mon, 25 Mar 2013 20:02:14 +0000 (20:02 +0000)]
Disable Execution Engine tests not supported by Hexagon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177896 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoreflect comment to the official reference
Shankar Easwaran [Mon, 25 Mar 2013 19:50:40 +0000 (19:50 +0000)]
reflect comment to the official reference

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177895 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll investigate them...
NAKAMURA Takumi [Mon, 25 Mar 2013 19:47:20 +0000 (19:47 +0000)]
Disable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll investigate them later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177894 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse direct types in PowerPC instruction patterns.
Ulrich Weigand [Mon, 25 Mar 2013 19:05:30 +0000 (19:05 +0000)]
Use direct types in PowerPC instruction patterns.

This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
instruction patterns, along the lines of Jakob Stoklund Olesen's
changes in r177835 for Sparc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse direct types in PowerPC Pat patterns.
Ulrich Weigand [Mon, 25 Mar 2013 19:04:58 +0000 (19:04 +0000)]
Use direct types in PowerPC Pat patterns.

This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
Pat patterns, along the lines of Jakob Stoklund Olesen's
changes in r177829 for Sparc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agox86 -- add the XTEST instruction
Dave Zarzycki [Mon, 25 Mar 2013 18:59:43 +0000 (18:59 +0000)]
x86 -- add the XTEST instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agox86 -- disassemble the REP/REPNE prefix when needed
Dave Zarzycki [Mon, 25 Mar 2013 18:59:38 +0000 (18:59 +0000)]
x86 -- disassemble the REP/REPNE prefix when needed

This fixes Apple bug: 13493622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unnecessary attributes from test case.
Chad Rosier [Mon, 25 Mar 2013 18:36:19 +0000 (18:36 +0000)]
Remove unnecessary attributes from test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177882 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove assert. There may be target-dependent attributes left.
Bill Wendling [Mon, 25 Mar 2013 17:42:20 +0000 (17:42 +0000)]
Remove assert. There may be target-dependent attributes left.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177878 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDocumentation: Replace dead link for binfmt_misc
Dmitri Gribenko [Mon, 25 Mar 2013 17:08:25 +0000 (17:08 +0000)]
Documentation: Replace dead link for binfmt_misc

Patch by Thomas Schwinge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177876 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[arm load/store optimizer] When trying to merge a base update load/store, make
Chad Rosier [Mon, 25 Mar 2013 16:29:20 +0000 (16:29 +0000)]
[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores.  This was already being done for loads.

Unfortunately, it is rather difficult to create a test case for this issue.  It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[tools][llvm-readobj] print the name of the section when iterating the symbol table...
Shankar Easwaran [Mon, 25 Mar 2013 16:06:51 +0000 (16:06 +0000)]
[tools][llvm-readobj] print the name of the section when iterating the symbol table / dynamic symbol table

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177873 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ELF] add elf_hash function to compute the hash value of a symbol in the dynamic...
Shankar Easwaran [Mon, 25 Mar 2013 16:02:10 +0000 (16:02 +0000)]
[ELF] add elf_hash function to compute the hash value of a symbol in the dynamic symbol table

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177872 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTeach cmake about the new Erlang GC files.
Duncan Sands [Mon, 25 Mar 2013 14:12:21 +0000 (14:12 +0000)]
Teach cmake about the new Erlang GC files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a GC plugin for Erlang
Yiannis Tsiouris [Mon, 25 Mar 2013 13:47:46 +0000 (13:47 +0000)]
Add a GC plugin for Erlang

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use add_llvm_definitions for adding warning flags. It makes it too hard
Duncan Sands [Mon, 25 Mar 2013 13:25:34 +0000 (13:25 +0000)]
Don't use add_llvm_definitions for adding warning flags.  It makes it too hard
to have them appear in the right order.  Instead append all warnings explicitly
to the language flags.  This was already the case for many warnings.  Fixes the
issue of -Wno-maybe-uninitialized not being effective because -Wall was being
placed after it rather than before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177866 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRefine fenv.h handling: check if the desired macros exist, before using
Joerg Sonnenberger [Mon, 25 Mar 2013 13:13:33 +0000 (13:13 +0000)]
Refine fenv.h handling: check if the desired macros exist, before using
it. NetBSD/ARM and TILE-Gx are examples for platforms that have an
unusable fenv.h and this avoids the need for a blacklist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177865 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAddress issues found by Duncan during post-commit review of r177856.
Arnaud A. de Grandmaison [Mon, 25 Mar 2013 11:47:38 +0000 (11:47 +0000)]
Address issues found by Duncan during post-commit review of r177856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)
Arnaud A. de Grandmaison [Mon, 25 Mar 2013 09:48:49 +0000 (09:48 +0000)]
InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)

This simplification happens at 2 places :
 - using the nsw attribute when the shl / mul is used by a sign test
 - when the shl / mul is compared for (in)equality to zero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChanged isNullOrUndef => IsNullOrUndef and isNoopInstruction => IsNoopInstruction...
Michael Gottesman [Mon, 25 Mar 2013 09:27:43 +0000 (09:27 +0000)]
Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMention the new TableGen pattern format in the release notes.
Jakob Stoklund Olesen [Mon, 25 Mar 2013 00:36:53 +0000 (00:36 +0000)]
Mention the new TableGen pattern format in the release notes.

Make threats about removing the old syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Fix handling of vector arguments
Justin Holewinski [Sun, 24 Mar 2013 21:17:47 +0000 (21:17 +0000)]
[NVPTX] Fix handling of vector arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoClean up Sparc patterns.
Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:04 +0000 (19:37 +0000)]
Clean up Sparc patterns.

The types of register variables no longer need to be specified in output
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow types to be omitted in output patterns.
Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:00 +0000 (19:37 +0000)]
Allow types to be omitted in output patterns.

This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow TableGen DAG arguments to be just a name.
Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:36:51 +0000 (19:36 +0000)]
Allow TableGen DAG arguments to be just a name.

DAG arguments can optionally be named:

  (dag node, node:$name)

With this change, the node is also optional:

  (dag node, node:$name, $name)

The missing node is treated as an UnsetInit, so the above is equivalent
to:

  (dag node, node:$name, ?:$name)

This syntax is useful in output patterns where we currently require the
types of variables to be repeated:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>;

This is preferable:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGettingStarted: Add Git clone instructions for compiler-rt and test-suite
Tobias Grosser [Sun, 24 Mar 2013 15:15:19 +0000 (15:15 +0000)]
GettingStarted: Add Git clone instructions for compiler-rt and test-suite

Contributed-by: Thomas Schwinge <thomas@codesourcery.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMinor cleanups. No functionality change.
Jakub Staszak [Sun, 24 Mar 2013 09:56:28 +0000 (09:56 +0000)]
Minor cleanups. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse dyn_cast instead of isa && cast.
Jakub Staszak [Sun, 24 Mar 2013 09:25:47 +0000 (09:25 +0000)]
Use dyn_cast instead of isa && cast.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGive Sparc instruction patterns direct types instead of register classes.
Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:20 +0000 (00:56 +0000)]
Give Sparc instruction patterns direct types instead of register classes.

Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow direct value types to be used in instruction 'set' patterns.
Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:16 +0000 (00:56 +0000)]
Allow direct value types to be used in instruction 'set' patterns.

This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC ZERO register needs a register number of 0.
Hal Finkel [Sat, 23 Mar 2013 22:06:07 +0000 (22:06 +0000)]
PPC ZERO register needs a register number of 0.

In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).

Thanks to Kai for reporting the problem!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoNote in PPCFunctionInfo VRSAVE spills
Hal Finkel [Sat, 23 Mar 2013 22:06:03 +0000 (22:06 +0000)]
Note in PPCFunctionInfo VRSAVE spills

In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMCize the bcl instruction in PPCAsmPrinter
Hal Finkel [Sat, 23 Mar 2013 20:53:15 +0000 (20:53 +0000)]
MCize the bcl instruction in PPCAsmPrinter

I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse direct types in Sparc def : Pat patterns.
Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:05 +0000 (20:35 +0000)]
Use direct types in Sparc def : Pat patterns.

The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.

This notation is also robust against adding more types to the IntRegs
register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow direct value types in pattern definitions.
Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:01 +0000 (20:35 +0000)]
Allow direct value types in pattern definitions.

Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleanup some unused reg. scavenger parameters in PPCRegisterInfo
Hal Finkel [Sat, 23 Mar 2013 19:36:47 +0000 (19:36 +0000)]
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo

These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake all unnamed RegisterClass TreePatternNodes typed MVT::i32.
Jakob Stoklund Olesen [Sat, 23 Mar 2013 18:08:44 +0000 (18:08 +0000)]
Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.

A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove dead PPC LR spilling code
Hal Finkel [Sat, 23 Mar 2013 17:14:27 +0000 (17:14 +0000)]
Remove dead PPC LR spilling code

The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPlug a memory leak in FileCheck when the input file is empty.
Benjamin Kramer [Sat, 23 Mar 2013 13:56:23 +0000 (13:56 +0000)]
Plug a memory leak in FileCheck when the input file is empty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove X86-dependent test into the right subdirectory.
Benjamin Kramer [Sat, 23 Mar 2013 09:35:44 +0000 (09:35 +0000)]
Move X86-dependent test into the right subdirectory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove the type legality check from the SelectionDAGBuilder when it lowers @llvm...
Owen Anderson [Sat, 23 Mar 2013 08:26:53 +0000 (08:26 +0000)]
Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.
Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA.
For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's.

NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook.  They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChange method name ClearRefCount => ClearKnownPositiveRefCount to match the name...
Michael Gottesman [Sat, 23 Mar 2013 05:46:19 +0000 (05:46 +0000)]
Change method name ClearRefCount => ClearKnownPositiveRefCount to match the name of the member that it is modifying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChanged the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRef...
Michael Gottesman [Sat, 23 Mar 2013 05:31:01 +0000 (05:31 +0000)]
Changed the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRefCount().

Now said method matches namewise every other method which refers to
the member KnownPositiveRefCount of the class PtrState.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix comparison of mixed signedness
Hal Finkel [Sat, 23 Mar 2013 00:07:29 +0000 (00:07 +0000)]
Fix comparison of mixed signedness

177774 broke the lld-x86_64-darwin11 builder; error:
error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long')
  for (SI = 0; SI < Scavenged.size(); ++SI)
               ~~ ^ ~~~~~~~~~~~~~~~~

Fix this by making SI also unsigned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[docs] Slight reword for precision.
Sean Silva [Fri, 22 Mar 2013 23:52:38 +0000 (23:52 +0000)]
[docs] Slight reword for precision.

The new wording cannot be construed as suggesting the use of
SmallVectorImpl<T> as e.g. a class member (just because the class
happens to be in an interface).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177778 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[docs] Document usage of SmallVectorImpl in interfaces.
Sean Silva [Fri, 22 Mar 2013 23:41:29 +0000 (23:41 +0000)]
[docs] Document usage of SmallVectorImpl in interfaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177775 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAllow the register scavenger to spill multiple registers
Hal Finkel [Fri, 22 Mar 2013 23:32:27 +0000 (23:32 +0000)]
Allow the register scavenger to spill multiple registers

This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSupport in AAEvaluator to print alias queries of loads/stores with TBAA tags.
Manman Ren [Fri, 22 Mar 2013 22:34:41 +0000 (22:34 +0000)]
Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.

Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries
between pointers do not include TBAA tags.

Add testing case for "placement new". TBAA currently says NoAlias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoKill every call to @clang.arc.use in the ARC contract phase.
John McCall [Fri, 22 Mar 2013 21:38:36 +0000 (21:38 +0000)]
Kill every call to @clang.arc.use in the ARC contract phase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUpdate test. There may be multiple catches, but those will be cleaned up.
Bill Wendling [Fri, 22 Mar 2013 20:36:39 +0000 (20:36 +0000)]
Update test. There may be multiple catches, but those will be cleaned up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd all clauses when merging the landing pads. Duplicates will be handled later on.
Bill Wendling [Fri, 22 Mar 2013 20:31:05 +0000 (20:31 +0000)]
Add all clauses when merging the landing pads. Duplicates will be handled later on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177757 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSwap the DIFile in DILexicalBlockFile out for the raw name/directory pair
David Blaikie [Fri, 22 Mar 2013 20:18:46 +0000 (20:18 +0000)]
Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair

This is the last change in transitioning all DIScopes to have a common prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177756 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoreorder the fields in DILexicalBlockFile to match the common prefix for DIScopes
David Blaikie [Fri, 22 Mar 2013 19:13:22 +0000 (19:13 +0000)]
reorder the fields in DILexicalBlockFile to match the common prefix for DIScopes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReverted r176374. In some cases the lit.site.cfg file does not get generated in tools...
Galina Kistanova [Fri, 22 Mar 2013 18:54:14 +0000 (18:54 +0000)]
Reverted r176374. In some cases the lit.site.cfg file does not get generated in tools/clang/tools/extra.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use the removed API.
Bill Wendling [Fri, 22 Mar 2013 18:49:53 +0000 (18:49 +0000)]
Don't use the removed API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177749 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert r177675. This is language-specific and shouldn't be in the API.
Bill Wendling [Fri, 22 Mar 2013 18:46:32 +0000 (18:46 +0000)]
Revert r177675. This is language-specific and shouldn't be in the API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177748 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
Jyotsna Verma [Fri, 22 Mar 2013 18:41:34 +0000 (18:41 +0000)]
Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRefactor out the DIFile parameter to DILexicalBlock to refer to the raw file/director...
David Blaikie [Fri, 22 Mar 2013 17:33:20 +0000 (17:33 +0000)]
Refactor out the DIFile parameter to DILexicalBlock to refer to the raw file/directory pair

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agofix small doc typo
Eli Bendersky [Fri, 22 Mar 2013 16:09:06 +0000 (16:09 +0000)]
fix small doc typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177737 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
Michel Danzer [Fri, 22 Mar 2013 15:24:16 +0000 (15:24 +0000)]
R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove ABI-duplicated call instruction patterns.
Ulrich Weigand [Fri, 22 Mar 2013 15:24:13 +0000 (15:24 +0000)]
Remove ABI-duplicated call instruction patterns.

We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux).  This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI.  And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions).  However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.

No change in generated code expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRename memrr ptrreg and offreg components.
Ulrich Weigand [Fri, 22 Mar 2013 14:59:13 +0000 (14:59 +0000)]
Rename memrr ptrreg and offreg components.

Currently, the sub-operand of a memrr address that corresponds to what
hardware considers the base register is called "offreg", while the
sub-operand that corresponds to the offset is called "ptrreg".

To avoid confusion, this patch simply swaps the named of those two
sub-operands and updates all uses.  No functional change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix swapped BasePtr and Offset in pre-inc memory addresses.
Ulrich Weigand [Fri, 22 Mar 2013 14:58:48 +0000 (14:58 +0000)]
Fix swapped BasePtr and Offset in pre-inc memory addresses.

PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result.  That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).

This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.

To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases.  (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTighten iaddroff ComplexPattern.
Ulrich Weigand [Fri, 22 Mar 2013 14:58:17 +0000 (14:58 +0000)]
Tighten iaddroff ComplexPattern.

The iaddroff ComplexPattern is supposed to recognize displacement
expressions that have been processed by a SelectAddressRegImm,
which means it needs to accept TargetConstant and TargetGlobalAddress
nodes.  Currently, it erroneously also accepts some other nodes,
in particular Constant and PPCISD::Lo.

While this problem is currently latent, it would cause wrong-code
bugs with a follow-on patch I'm about to commit, so this patch
tightens the ComplexPattern.  The equivalent change is made in
PPCDAGToDAGISel::Select, where pre-inc load patterns are handled
(as opposed to store patterns, the loads are handled in C++ code
without making use of the .td ComplexPattern).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove the xaddroff ComplexPattern.
Ulrich Weigand [Fri, 22 Mar 2013 14:57:48 +0000 (14:57 +0000)]
Remove the xaddroff ComplexPattern.

The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns.  This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics
Michel Danzer [Fri, 22 Mar 2013 14:09:10 +0000 (14:09 +0000)]
R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics

Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.

Tested on SI and RS880.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[asan] Change the way we report the alloca frame on stack-buff-overflow.
Kostya Serebryany [Fri, 22 Mar 2013 10:37:20 +0000 (10:37 +0000)]
[asan] Change the way we report the alloca frame on stack-buff-overflow.

Before: the function name was stored by the compiler as a constant string
and the run-time was printing it.
Now: the PC is stored instead and the run-time prints the full symbolized frame.
This adds a couple of instructions into every function with non-empty stack frame,
but also reduces the binary size because we store less strings (I saw 2% size reduction).
This change bumps the asan ABI version to v3.

llvm part.

Example of report (now):
==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8
READ of size 1 at 0x7fffa77cf1c5 thread T0
    #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20
    #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24
    #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28
    #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32
    #4 0x41eee0 in main stack-oob-frames.cc:38
    #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c)
    #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c)
Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame
    #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12  <<<<<<<<<<<<<< this is new
  This frame has 6 object(s):
    [32, 36) 'frame.addr'
    [96, 104) 'a.addr'
    [160, 168) 'b.addr'
    [224, 232) 'c.addr'
    [288, 292) 's'
    [352, 360) 'd'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177724 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agotsan: fix the test
Dmitry Vyukov [Fri, 22 Mar 2013 09:04:01 +0000 (09:04 +0000)]
tsan: fix the test
Add missed file from r177717 commit that adds __tsan_vptr_read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agotsan: handle vptr loads specially
Dmitry Vyukov [Fri, 22 Mar 2013 08:51:22 +0000 (08:51 +0000)]
tsan: handle vptr loads specially
This is required to determine ctor/dtor vs virtual call races.
http://llvm-reviews.chandlerc.com/D566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177717 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix llvm::removeUnreachableBlocks to handle unreachable loops.
Evgeniy Stepanov [Fri, 22 Mar 2013 08:43:04 +0000 (08:43 +0000)]
Fix llvm::removeUnreachableBlocks to handle unreachable loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177713 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: Improve the result bitvect type when folding (cmp pred (load (gep GV...
Arnaud A. de Grandmaison [Fri, 22 Mar 2013 08:25:01 +0000 (08:25 +0000)]
InstCombine: Improve the result bitvect type when folding (cmp pred (load (gep GV, i)) C) to a bit test.

The original code used i32, and i64 if legal. This introduced unneeded
casts when they aren't legal, or when the index variable i has another
type. In order of preference: try to use i's type; use the smallest
fitting legal type (using an added DataLayout method); default to i32.
A testcase checks that this works when the index gep operand is i16.

Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com>
Reviewed by : Duncan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177712 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove ScavengedRC from RegisterScavenging
Hal Finkel [Fri, 22 Mar 2013 07:27:44 +0000 (07:27 +0000)]
Remove ScavengedRC from RegisterScavenging

ScavengedRC was a dead private variable (set, but not otherwise used). No
functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReorder the DIFile field in DILexicalBlock to become a prefix common with other DIScopes
David Blaikie [Fri, 22 Mar 2013 05:47:44 +0000 (05:47 +0000)]
Reorder the DIFile field in DILexicalBlock to become a prefix common with other DIScopes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8