Michael Gottesman [Sun, 17 Mar 2013 08:42:58 +0000 (08:42 +0000)]
The promised test case for r175939.
This test makes sure that the ObjCARC escape analysis looks at the uses of
instructions which copy the block pointer value by checking all four cases where
that can occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sun, 17 Mar 2013 04:43:44 +0000 (04:43 +0000)]
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sat, 16 Mar 2013 23:02:31 +0000 (23:02 +0000)]
Remove FIXMEs in PPC test cases related to unaligned loads/stores
As pointed out by Bill in response to r177160, these two FIXMEs
can also be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sat, 16 Mar 2013 22:50:51 +0000 (22:50 +0000)]
Remove PPC avoidWriteAfterWrite callback
As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Sat, 16 Mar 2013 18:58:57 +0000 (18:58 +0000)]
Change the default latency for implicit defs.
Implicit defs are not currently positional and not modeled by the
per-operand machine model. Unfortunately, we treat defs that are part
of the architectural instruction description, like flags, the same as
other implicit defs. Really, they should have a fixed MachineInstr
layout and probably shouldn't be "implicit" at all.
For now, we'll change the default latency to be the max operand
latency. That will give flag setting operands full latency for x86
folded loads. Other kinds of "fake" implicit defs don't occur prior to
regalloc anyway, and we would like them to go away postRegAlloc as
well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Sat, 16 Mar 2013 18:58:55 +0000 (18:58 +0000)]
Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.
Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226
91177308-0d34-0410-b5e6-
96231b3b80d8
Sean Silva [Sat, 16 Mar 2013 16:58:20 +0000 (16:58 +0000)]
[docs] Discuss a potential bug to be aware of.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177224
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Sat, 16 Mar 2013 15:00:51 +0000 (15:00 +0000)]
Test case for graceful handling of long file names on Windows. Patch thanks to Paul Robinson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177223
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 16 Mar 2013 03:44:31 +0000 (03:44 +0000)]
Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Sat, 16 Mar 2013 00:02:17 +0000 (00:02 +0000)]
Define more SchedWrites for annotating X86 instructions.
Since almost all X86 instructions can fold loads, use a multiclass to
define register/memory pairs of SchedWrites.
An X86FoldableSchedWrite represents the register version of an
instruction. It holds a reference to the SchedWrite to use when the
instruction folds a load.
This will be used inside multiclasses that define rr and rm instruction
versions together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 15 Mar 2013 22:51:13 +0000 (22:51 +0000)]
Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:
let SchedRW = ... in {
...
}
Which is now possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Dunbar [Fri, 15 Mar 2013 20:16:59 +0000 (20:16 +0000)]
[ADT] Fix StringSet::insert() to not allocate on every lookup.
- The previous implementation always constructed the StringMap entry, even if
the key was present in the set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177178
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Fri, 15 Mar 2013 19:25:47 +0000 (19:25 +0000)]
[Support][Path][Windows] Fix dangling else. Don't call CloseHandle when CloseFD is false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177175
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Fri, 15 Mar 2013 18:31:01 +0000 (18:31 +0000)]
ARM cost model: Fix costs for some vector selects
I was too pessimistic in r177105. Vector selects that fit into a legal register
type lower just fine. I was mislead by the code fragment that I was using. The
stores/loads that I saw in those cases came from lowering the conditional off
an address.
Changing the code fragment to:
%T0_3 = type <8 x i18>
%T1_3 = type <8 x i1>
define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2,
%T1_3* %blend, %T0_3* %storeaddr) {
%v0 = load %T0_3* %loadaddr
%v1 = load %T0_3* %loadaddr2
==> FROM:
;%c = load %T1_3* %blend
==> TO:
%c = icmp slt %T0_3 %v0, %v1
==> USE:
%r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1
store %T0_3 %r, %T0_3* %storeaddr
ret void
}
revealed this mistake.
radar://
13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170
91177308-0d34-0410-b5e6-
96231b3b80d8
Silviu Baranga [Fri, 15 Mar 2013 18:28:25 +0000 (18:28 +0000)]
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Fri, 15 Mar 2013 17:27:39 +0000 (17:27 +0000)]
ARM: Fix an old refacto.
Fixes PR15520.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Fri, 15 Mar 2013 15:27:13 +0000 (15:27 +0000)]
Enable unaligned memory access on PPC for scalar types
Unaligned access is supported on PPC for non-vector types, and is generally
more efficient than manually expanding the loads and stores.
A few of the existing test cases were using expanded unaligned loads and stores
to test other features (like load/store with update), and for these test cases,
unaligned access remains disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Fri, 15 Mar 2013 15:10:47 +0000 (15:10 +0000)]
ARM cost model: Fix cost of fptrunc and fpext instructions
A vector fptrunc and fpext simply gets split into scalar instructions.
radar://
13192358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Fri, 15 Mar 2013 13:21:21 +0000 (13:21 +0000)]
Protect PPC Altivec patterns with a predicate
In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.
No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec
support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Fri, 15 Mar 2013 07:27:49 +0000 (07:27 +0000)]
Fixup for r176933: more careful setup of path to llvm-symbolizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177144
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 15 Mar 2013 06:01:42 +0000 (06:01 +0000)]
Use NumBaseBits in a few more places in SmallBitVector instead of recalculating it. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177142
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 15 Mar 2013 05:51:57 +0000 (05:51 +0000)]
Fix the FDE encoding to be relative on ELF.
This is a very late complement to r130637 which fixed this on x86_64. Fixes
pr15448.
Since it looks like that every elf architecture uses this encoding when using
cfi, make it the default for elf. Just exclude mips64el. It has a lovely
.ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary
content of the .eh_frame produced by llc. Oblige it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Fri, 15 Mar 2013 05:06:04 +0000 (05:06 +0000)]
Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.
I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 15 Mar 2013 00:43:00 +0000 (00:43 +0000)]
Turn anonymous type in anonymous union warning back on after cleaning up
issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177136
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 15 Mar 2013 00:42:55 +0000 (00:42 +0000)]
Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Fri, 15 Mar 2013 00:10:23 +0000 (00:10 +0000)]
Add a triple to the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177131
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Thu, 14 Mar 2013 23:49:44 +0000 (23:49 +0000)]
Unaligned loads should use the VMOVUPS opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Thu, 14 Mar 2013 23:11:07 +0000 (23:11 +0000)]
Remove some unused variables to clean the Clang -Werror build
(these were added in r177089)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 23:09:19 +0000 (23:09 +0000)]
[mips] Set isAllocatable bit of unallocatable register classes to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Thu, 14 Mar 2013 22:47:01 +0000 (22:47 +0000)]
Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 14 Mar 2013 22:42:17 +0000 (22:42 +0000)]
Prepare for adding InstrSchedModel annotations to X86 instructions.
The new InstrSchedModel is easier to use than the instruction
itineraries. It will be used to model instruction latency and throughput
in modern Intel microarchitectures like Sandy Bridge.
InstrSchedModel should be able to coexist with instruction itinerary
classes, but for cleanliness we should switch the Atom processor model
to the new InstrSchedModel as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122
91177308-0d34-0410-b5e6-
96231b3b80d8
Reed Kotler [Thu, 14 Mar 2013 22:02:09 +0000 (22:02 +0000)]
Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup.
Normally you need to add register classes and then call
computeRegisterProperties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Thu, 14 Mar 2013 21:31:09 +0000 (21:31 +0000)]
LoopVectorizer: Insert some white space to make test case more readable
Also remove some unneeded function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177114
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 14 Mar 2013 21:25:04 +0000 (21:25 +0000)]
[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handle
the win64 calling convention.
rdar://
13423768
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Thu, 14 Mar 2013 21:21:50 +0000 (21:21 +0000)]
MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.
This allows SandyBridge to be expressed naturally, which will be
checked in shortly.
def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 14 Mar 2013 21:15:20 +0000 (21:15 +0000)]
Move estimateStackSize from ARM into MachineFrameInfo
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 14 Mar 2013 20:33:40 +0000 (20:33 +0000)]
Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.
This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 14 Mar 2013 20:21:47 +0000 (20:21 +0000)]
Use frame-index scavenging for PPC register spilling
Make requiresFrameIndexScavenging return true, and create virtual registers in
the spilling code instead of using the register scavenger directly. This makes
the target-level code simpler, and importantly, delays the scavenging until
after callee-saved register processing (which will be important for later
changes).
Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with
the other related functions). This makes it clear that it always returns true.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 14 Mar 2013 19:34:32 +0000 (19:34 +0000)]
Not all PPC functions with a frame pointer need a RS spill slot
We used to add a spill slot for the register scavenger whenever the function
has a frame pointer. This is unnecessarily conservative: We may need the spill
slot for dynamic stack allocations, and functions with dynamic stack
allocations always have a FP, but we might also have a FP for other reasons
(such as the user explicitly disabling frame-pointer elimination), and we don't
necessarily need a spill slot for those functions.
The structsinregs test needed adjustment because it disables FP elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Thu, 14 Mar 2013 19:17:02 +0000 (19:17 +0000)]
ARM cost model: Increase cost of some vector selects we do terrible on
By terrible I mean we store/load from the stack.
This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update)
where we decide to vectorize a loop with a VF of 8 resulting in a 25%
degradation on a cortex-a8.
LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32
LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32
The bug that tracks the CodeGen part is PR14868.
radar://
13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 19:09:52 +0000 (19:09 +0000)]
[mips] Fix filename in comment and delete unnecessary lines of code.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104
91177308-0d34-0410-b5e6-
96231b3b80d8
Jyotsna Verma [Thu, 14 Mar 2013 19:08:03 +0000 (19:08 +0000)]
Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Thu, 14 Mar 2013 19:01:58 +0000 (19:01 +0000)]
Add missing asserts flag to test - it uses debug flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177102
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 19:01:00 +0000 (19:01 +0000)]
Android uses cacheflush(long start, long end, long flags) for MIPS.
Patch by Stephen Hines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177101
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Thu, 14 Mar 2013 18:54:36 +0000 (18:54 +0000)]
LoopVectorize: Invert case when we use a vector cmp value to query select cost
We generate a select with a vectorized condition argument when the condition is
NOT loop invariant. Not the other way around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177098
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 18:46:46 +0000 (18:46 +0000)]
Add back lines which were accidentally deleted in CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 18:39:25 +0000 (18:39 +0000)]
[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 14 Mar 2013 18:38:31 +0000 (18:38 +0000)]
Add a comment about overlapping PPC frame offsets
I don't think that it is otherwise clear how the overlapping offsets
are processed into distinct spill slots. Comment that this is done
in processFunctionBeforeFrameFinalized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 18:33:23 +0000 (18:33 +0000)]
[mips] Rename functions and variables to start with proper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 18:28:19 +0000 (18:28 +0000)]
Add header file MipsISelDAGToDAG.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 14 Mar 2013 18:27:31 +0000 (18:27 +0000)]
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089
91177308-0d34-0410-b5e6-
96231b3b80d8
Shuxin Yang [Thu, 14 Mar 2013 18:08:26 +0000 (18:08 +0000)]
Perform factorization as a last resort of unsafe fadd/fsub simplification.
Rules include:
1)1 x*y +/- x*z => x*(y +/- z)
(the order of operands dosen't matter)
2) y/x +/- z/x => (y +/- z)/x
The transformation is disabled if the new add/sub expr "y +/- z" is a
denormal/naz/inifinity.
rdar://
12911472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177088
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Thu, 14 Mar 2013 17:54:13 +0000 (17:54 +0000)]
Test that we emit a DW_AT_location for self captured by a block.
This is the backend part of a CFE test with the same name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177087
91177308-0d34-0410-b5e6-
96231b3b80d8
Vincent Lejeune [Thu, 14 Mar 2013 15:50:45 +0000 (15:50 +0000)]
R600: Factorize code handling Const Read Port limitation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Thu, 14 Mar 2013 12:38:58 +0000 (12:38 +0000)]
[ASan] emit instrumentation for initialization order checking by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177063
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Thu, 14 Mar 2013 11:32:24 +0000 (11:32 +0000)]
PR14972: SROA vs. GVN exposed a really bad bug in SROA.
The fundamental problem is that SROA didn't allow for overly wide loads
where the bits past the end of the alloca were masked away and the load
was sufficiently aligned to ensure there is no risk of page fault, or
other trapping behavior. With such widened loads, SROA would delete the
load entirely rather than clamping it to the size of the alloca in order
to allow mem2reg to fire. This was exposed by a test case that neatly
arranged for GVN to run first, widening certain loads, followed by an
inline step, and then SROA which miscompiles the code. However, I see no
reason why this hasn't been plaguing us in other contexts. It seems
deeply broken.
Diagnosing all of the above took all of 10 minutes of debugging. The
really annoying aspect is that fixing this completely breaks the pass.
;] There was an implicit reliance on the fact that no loads or stores
extended past the alloca once we decided to rewrite them in the final
stage of SROA. This was used to encode information about whether the
loads and stores had been split across multiple partitions of the
original alloca. That required threading explicit tracking of whether
a *use* of a partition is split across multiple partitions.
Once that was done, another problem arose: we allowed splitting of
integer loads and stores iff they were loads and stores to the entire
alloca. This is a really arbitrary limitation, and splitting at least
some integer loads and stores is crucial to maximize promotion
opportunities. My first attempt was to start removing the restriction
entirely, but currently that does Very Bad Things by causing *many*
common alloca patterns to be fully decomposed into i8 operations and
lots of or-ing together to produce larger integers on demand. The code
bloat is terrifying. That is still the right end-goal, but substantial
work must be done to either merge partitions or ensure that small i8
values are eagerly merged in some other pass. Sadly, figuring all this
out took essentially all the time and effort here.
So the end result is that we allow splitting only when the load or store
at least covers the alloca. That ensures widened loads and stores don't
hurt SROA, and that we don't rampantly decompose operations more than we
have previously.
All of this was already fairly well tested, and so I've just updated the
tests to cover the wide load behavior. I can add a test that crafts the
pass ordering magic which caused the original PR, but that seems really
brittle and to provide little benefit. The fundamental problem is that
widened loads should Just Work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177055
91177308-0d34-0410-b5e6-
96231b3b80d8
Joerg Sonnenberger [Thu, 14 Mar 2013 08:01:36 +0000 (08:01 +0000)]
Add two of the float related ARM-specific entries for e_flags needed for
linkers to interact with GNU ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177016
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Mar 2013 07:47:43 +0000 (07:47 +0000)]
Fix the name of a variable to match its declaration. Fixes build failure from r177014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Mar 2013 07:40:52 +0000 (07:40 +0000)]
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Mar 2013 07:09:57 +0000 (07:09 +0000)]
Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Thu, 14 Mar 2013 06:57:42 +0000 (06:57 +0000)]
Fix PR15309
- Fix the typo on type checking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010
91177308-0d34-0410-b5e6-
96231b3b80d8
Jiong Wang [Thu, 14 Mar 2013 05:43:59 +0000 (05:43 +0000)]
test commit: remove blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177009
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Thu, 14 Mar 2013 05:28:10 +0000 (05:28 +0000)]
Remove a change to the debug info in this test, that I made while testing
something else and forgot to remove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177007
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Thu, 14 Mar 2013 05:23:30 +0000 (05:23 +0000)]
Try using %S to find the emitted .gcno file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177006
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Thu, 14 Mar 2013 05:19:12 +0000 (05:19 +0000)]
Remove accidentally committed debug line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177005
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Thu, 14 Mar 2013 05:13:26 +0000 (05:13 +0000)]
Refactor GCOV's six constructor arguments into a struct with a getter that
constructs default arguments. It can now take default arguments from
cl::opt'ions. Add a new -default-gcov-version=... option, and actually test it!
Sink the reverse-order of the version into GCOVProfiling, hiding it from our
users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177002
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Thu, 14 Mar 2013 01:26:17 +0000 (01:26 +0000)]
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176997
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Thu, 14 Mar 2013 00:33:37 +0000 (00:33 +0000)]
[Support][Test] Missed this in the API change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176996
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Thu, 14 Mar 2013 00:20:10 +0000 (00:20 +0000)]
[Support] Fix lifetime of file descriptors when using MemoryBuffer.
Clients of MemoryBuffer::getOpenFile expect it not to take ownership of the file
descriptor passed in. So don't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176995
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Wed, 13 Mar 2013 22:55:42 +0000 (22:55 +0000)]
No functionality change. Rename emitGCNO() to the more sensible
emitProfileNotes(), similar to emitProfileArcs(). Also update its comment.
Also add a comment on Version[4] (there will be another comment in clang later),
and compress lines that exceeded 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176994
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 13 Mar 2013 22:52:59 +0000 (22:52 +0000)]
Simplify file/directory name handling in DILexicalBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176993
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 13 Mar 2013 22:33:09 +0000 (22:33 +0000)]
Remove an extra operand to a DIFile metadata entry
(extra cleanup/fallout from r176983 - not sure why I didn't catch this locally)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176988
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 13 Mar 2013 22:26:59 +0000 (22:26 +0000)]
Reset some of the target options which affect code generation.
This doesn't reset all of the target options within the TargetOptions
object. This is because some of those are ABI-specific and must be determined if
it's okay to change those on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 13 Mar 2013 22:23:51 +0000 (22:23 +0000)]
Simplify directory name handling in DILexicalBlockFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176984
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 13 Mar 2013 22:05:21 +0000 (22:05 +0000)]
Remove the unused 4th operand for DIFile debug info metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176983
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 13 Mar 2013 21:18:46 +0000 (21:18 +0000)]
Make LTO codegen use a PassManager, rather than a FunctionPassManager, for the
codegen passes. This brings it in to line with clang and llc's codegen setup,
and tidies up the code.
If I understand correctly, adding ModulePasses to a FunctionPassManager is
bogus. It only seems to explode if an added ModulePass depends on a
FunctionPass though, which might be why this code has survived so long.
Fixes <rdar://problem/
13386816>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176977
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Wed, 13 Mar 2013 20:50:23 +0000 (20:50 +0000)]
Simplify CMake rules in HandleLLVMOptions module.
Summary: No functionality change.
Reviewers: Bigcheese
Reviewed By: Bigcheese
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176973
91177308-0d34-0410-b5e6-
96231b3b80d8
Reed Kotler [Wed, 13 Mar 2013 20:20:08 +0000 (20:20 +0000)]
Add some additonal attribute helper functions. Test will be on follow
up putback to clang for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176968
91177308-0d34-0410-b5e6-
96231b3b80d8
Vincent Lejeune [Wed, 13 Mar 2013 20:13:25 +0000 (20:13 +0000)]
R600: Remove unused Outputs variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176967
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Wed, 13 Mar 2013 18:41:27 +0000 (18:41 +0000)]
No functionality change. Use unreachable in getCUOffset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176963
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Wed, 13 Mar 2013 18:33:41 +0000 (18:33 +0000)]
No functionality change. Use unreachable in getCompileUnit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176962
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 13 Mar 2013 18:11:17 +0000 (18:11 +0000)]
Check register classes also when changing them.
We have the same assertion in createVirtualRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176959
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Wed, 13 Mar 2013 16:25:55 +0000 (16:25 +0000)]
ARM cost model: Add test case to make sure we would notice a change in CodeGen
In r176898 I updated the cost model to reflect the fact that sext/zext/cast on
v8i32 <-> v8i8 and v16i32 <-> v16i8 are expensive.
This test case is so that we make sure to update the cost model once we fix
CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176955
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnaud A. de Grandmaison [Wed, 13 Mar 2013 14:40:37 +0000 (14:40 +0000)]
Fix a performance regression when combining to smaller types in icmp (shl %v, C1), C2 :
Only combine when the shl is only used by the icmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176950
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 13 Mar 2013 13:50:47 +0000 (13:50 +0000)]
Add one more overload to make VS2008's debug mody happy.
sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176946
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Wed, 13 Mar 2013 09:35:18 +0000 (09:35 +0000)]
Add llvm-symbolizer as test dependency.
It is required when building tests with ASan or MSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176941
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Wed, 13 Mar 2013 06:58:09 +0000 (06:58 +0000)]
Set symbolizer path in the test environment.
This is needed to get symbolized stack traces when running LLVM tests under (A|M)San.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176933
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Wed, 13 Mar 2013 06:16:33 +0000 (06:16 +0000)]
lit.TestFormats.GoogleTest: Honor LitConfig.noExecute, or --no-execute were ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176930
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 13 Mar 2013 00:54:29 +0000 (00:54 +0000)]
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 13 Mar 2013 00:01:35 +0000 (00:01 +0000)]
Refactor filename/directory in DICompileUnit into a DIFile
This is the next step towards making the metadata for DIScopes have a common
prefix rather than having to delegate based on their tag type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176913
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Beaumont-Gay [Tue, 12 Mar 2013 23:55:24 +0000 (23:55 +0000)]
Don't crash if write_impl() leaves less buffer space available than expected.
This was tickled by a Clang diagnostic; Clang test case to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176911
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 12 Mar 2013 22:43:04 +0000 (22:43 +0000)]
Remove unused "isMain" field from DICompileUnit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176910
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 12 Mar 2013 22:32:39 +0000 (22:32 +0000)]
[Support][Path] Don't inf loop if creating the parent directory fails.
Patch by Paul Robinson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176908
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 12 Mar 2013 22:25:36 +0000 (22:25 +0000)]
Update debug info test cases with empty SplitDebugFilename field.
This could be 'null' or the empty string, DIDescriptor::getStringField
coalesces the two cases anyway so it's just a matter of legible/efficient
representation.
The change in behavior of the DICompileUnit::get* functions could be
subsumed by the full verification check - but ideally that should just be an
assertion if we could front-load the actual debug info metadata failure paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176907
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Tue, 12 Mar 2013 21:19:22 +0000 (21:19 +0000)]
ARM cost model: Increase the cost for vector casts that use the stack
Increase the cost of v8/v16-i8 to v8/v16-i32 casts and truncates as the backend
currently lowers those using stack accesses.
This was responsible for a significant degradation on
MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1
where we vectorize one loop to a vector factor of 16. After this patch we select
a vector factor of 4 which will generate reasonable code.
unsigned char cle[32];
void test(short c) {
unsigned short compte;
for (compte = 0; compte <= 31; compte++) {
cle[compte] = cle[compte] ^ c;
}
}
radar://
13220512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176898
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Tue, 12 Mar 2013 20:17:00 +0000 (20:17 +0000)]
Debug Info: use SmallVector instead of std::vector in MCDwarfDirsCUMap and MCDwarfFilesCUMap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176893
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 12 Mar 2013 19:28:19 +0000 (19:28 +0000)]
[Support][MemoryBuffer] Use sys::fs::mapped_file_region instead of sys::Path::MapInFilePages.
This gives us memory mapped file I/O on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176886
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 12 Mar 2013 19:04:24 +0000 (19:04 +0000)]
Correct invalid debug info metadata
Code review feedback on r176838 by Patrik Hägglund.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176884
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Tue, 12 Mar 2013 18:27:15 +0000 (18:27 +0000)]
Debug Info: use DW_FORM_ref_addr instead of DW_FORM_ref4 if the referenced DIE
belongs to a different compile unit.
DW_FORM_ref_addr should be used for cross compile-unit reference.
When compiling a large application, we got a dwarfdump verification error where
abstract_origin points to nowhere.
This error can't be reproduced on any testing case in MultiSource.
We may have other cases where we use DW_FORM_ref4 unconditionally.
rdar://problem/
13370501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176882
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Relph [Tue, 12 Mar 2013 18:17:18 +0000 (18:17 +0000)]
Avoid generating ISD::SELECT for vector operands to SIGN_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881
91177308-0d34-0410-b5e6-
96231b3b80d8