oota-llvm.git
11 years agoUse SmallVectorImpl instead of SmallVector as method argument to avoid specifying...
Craig Topper [Wed, 3 Jul 2013 05:16:59 +0000 (05:16 +0000)]
Use SmallVectorImpl instead of SmallVector as method argument to avoid specifying vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185513 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse SmallVectorImpl instead of SmallVector for iterators and references to avoid...
Craig Topper [Wed, 3 Jul 2013 05:11:49 +0000 (05:11 +0000)]
Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185512 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse SmallVectorImpl::iterator/const_iterator instead of SmallVector
Eric Christopher [Wed, 3 Jul 2013 05:01:24 +0000 (05:01 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector
to avoid specifying the vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185511 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifyi...
Craig Topper [Wed, 3 Jul 2013 04:42:33 +0000 (04:42 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185509 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoIntroduce some typedefs for DenseMaps containing SmallVectors so the vector size...
Craig Topper [Wed, 3 Jul 2013 04:40:27 +0000 (04:40 +0000)]
Introduce some typedefs for DenseMaps containing SmallVectors so the vector size doesn't have to repeated when creating iterators for the DenseMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185508 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReturn SmallVectorImpl& instead of SmallVector& in a couple places to avoid having...
Craig Topper [Wed, 3 Jul 2013 04:30:58 +0000 (04:30 +0000)]
Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid having to specify the vector size in multiple places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185507 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a space between type and variable name. No functional change.
Craig Topper [Wed, 3 Jul 2013 04:27:31 +0000 (04:27 +0000)]
Add a space between type and variable name. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185506 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse SmallVectorImpl& instead of SmallVector& to avoid needlessly respecifying the...
Craig Topper [Wed, 3 Jul 2013 04:24:43 +0000 (04:24 +0000)]
Use SmallVectorImpl& instead of SmallVector& to avoid needlessly respecifying the small vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185505 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifyi...
Craig Topper [Wed, 3 Jul 2013 04:17:25 +0000 (04:17 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185504 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChange the gettimeofday test to only test on a posix platform.
Michael Gottesman [Wed, 3 Jul 2013 04:15:22 +0000 (04:15 +0000)]
Change the gettimeofday test to only test on a posix platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185503 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded support in FunctionAttrs for adding relevant function/argument attributes for...
Michael Gottesman [Wed, 3 Jul 2013 04:00:54 +0000 (04:00 +0000)]
Added support in FunctionAttrs for adding relevant function/argument attributes for the posix call gettimeofday.

This implies annotating it as nounwind and its arguments as nocapture. To be
conservative, we do not annotate the arguments with noalias since some platforms
do not have restrict on the declaration for gettimeofday.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185502 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded posix function gettimeofday to LibFunc::Func for all platforms but Windows.
Michael Gottesman [Wed, 3 Jul 2013 04:00:51 +0000 (04:00 +0000)]
Added posix function gettimeofday to LibFunc::Func for all platforms but Windows.

*NOTE* In a recent version of posix, they added the restrict keyword to the
arguments for this function. From some spelunking it seems that on some
platforms, the call has restrict on its arguments and others it does not. Thus I
left off the restrict keyword from the function prototype in the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185501 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAvoid doing a lot of computation when we have multiple ranges and
Eric Christopher [Wed, 3 Jul 2013 02:23:53 +0000 (02:23 +0000)]
Avoid doing a lot of computation when we have multiple ranges and
avoid adding information for the debug_inlined section when it isn't
going to be emitted anyhow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185500 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]
NAKAMURA Takumi [Wed, 3 Jul 2013 02:20:49 +0000 (02:20 +0000)]
SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185499 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove iterator to where it's used and update comments.
Eric Christopher [Wed, 3 Jul 2013 01:57:28 +0000 (01:57 +0000)]
Move iterator to where it's used and update comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185498 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove instance variable before experimental section.
Eric Christopher [Wed, 3 Jul 2013 01:57:26 +0000 (01:57 +0000)]
Move instance variable before experimental section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185497 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix typo to make grep for DW_AT_comp_dir work without case-insensitive
Eric Christopher [Wed, 3 Jul 2013 01:57:23 +0000 (01:57 +0000)]
Fix typo to make grep for DW_AT_comp_dir work without case-insensitive
grep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185496 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unnecessary forward declare.
Eric Christopher [Wed, 3 Jul 2013 01:57:20 +0000 (01:57 +0000)]
Remove unnecessary forward declare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185495 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a helpful comment.
Eric Christopher [Wed, 3 Jul 2013 01:22:29 +0000 (01:22 +0000)]
Add a helpful comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185492 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoaddConstantValue, addConstantFPValue never returned anything but
Eric Christopher [Wed, 3 Jul 2013 01:08:30 +0000 (01:08 +0000)]
addConstantValue, addConstantFPValue never returned anything but
true, so remove the return value and propagate accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185490 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTrying to fix the bots
Manman Ren [Wed, 3 Jul 2013 00:16:11 +0000 (00:16 +0000)]
Trying to fix the bots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185489 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDebug Info: use module flag to set up Dwarf version.
Manman Ren [Tue, 2 Jul 2013 23:40:10 +0000 (23:40 +0000)]
Debug Info: use module flag to set up Dwarf version.

Correctly handles ref_addr depending on the Dwarf version. Emit Dwarf with
version from module flag.

TODO: turn on/off features depending on the Dwarf version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185484 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix comment.
Eric Christopher [Tue, 2 Jul 2013 21:36:07 +0000 (21:36 +0000)]
Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185480 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFixed typo in LangRef where we were using _'' to quote instead of the correct _.
Michael Gottesman [Tue, 2 Jul 2013 21:32:56 +0000 (21:32 +0000)]
Fixed typo in LangRef where we were using _'' to quote instead of the correct _.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185479 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] PR16512 - Support TLS call sequences in the asm parser
Ulrich Weigand [Tue, 2 Jul 2013 21:31:59 +0000 (21:31 +0000)]
[PowerPC] PR16512 - Support TLS call sequences in the asm parser

This patch now adds support for recognizing TLS call sequences in
the asm parser.  This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop.  That pattern is used for the
asm parser only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Rework TLS call operand processing
Ulrich Weigand [Tue, 2 Jul 2013 21:31:04 +0000 (21:31 +0000)]
[PowerPC] Rework TLS call operand processing

As part of the global-dynamic and local-dynamic TLS sequences, we need
to use a special form of the call instruction:

 bl __tls_get_addr(sym@tlsld)
 bl __tls_get_addr(sym@tlsgd)

which generates two fixups.  The current implementation of this causes
problems with recognizing this form in the asm parser.  To fix this,
this patch reworks operand processing for this special form by using
a single operand to hold both __tls_get_addr and sym@tlsld and defining
a print method to output the above form, and an encoding method to
generate the two fixups.

As a side simplification, the patch replaces the two instruction
patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS,
since the patterns already operate in an identical fashion (whether
we have a local-dynamic or global-dynamic symbol is already encoded
in the symbol modifier).

No change in code generation intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185477 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
Ulrich Weigand [Tue, 2 Jul 2013 21:29:06 +0000 (21:29 +0000)]
[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD

The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.

To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout.  (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSystemZ: Fold variable into assertion.
Benjamin Kramer [Tue, 2 Jul 2013 21:17:31 +0000 (21:17 +0000)]
SystemZ: Fold variable into assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185475 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.
Jyotsna Verma [Tue, 2 Jul 2013 19:21:43 +0000 (19:21 +0000)]
Add 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185465 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Support TLS variables in debug info
Ulrich Weigand [Tue, 2 Jul 2013 18:47:35 +0000 (18:47 +0000)]
[PowerPC] Support TLS variables in debug info

This adds an implementation of getDebugThreadLocalSymbol for
(64-bit) PowerPC.  This needs to return a generic MCExpr
since on ppc64, we need to add a bias of 0x8000 to the
value returned by the R_PPC64_DTPREL64 relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr
Ulrich Weigand [Tue, 2 Jul 2013 18:47:09 +0000 (18:47 +0000)]
[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr

This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[DebugInfo] Hold generic MCExpr in AddrPool
Ulrich Weigand [Tue, 2 Jul 2013 18:46:46 +0000 (18:46 +0000)]
[DebugInfo] Hold generic MCExpr in AddrPool

This changes the AddrPool infrastructure to enable it to hold
generic MCExpr expressions, not just MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185459 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr values
Ulrich Weigand [Tue, 2 Jul 2013 18:46:26 +0000 (18:46 +0000)]
[DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr values

This partially reverts r185202 and restores DIELabel to hold plain
MCSymbol references.  Instead, we add a new subclass DIEExpr of
DIEValue that can hold generic MCExpr references.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185458 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDebug Info: cleanup
Manman Ren [Tue, 2 Jul 2013 18:37:35 +0000 (18:37 +0000)]
Debug Info: cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185456 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert (most of) r185393 and r185395.
Jakob Stoklund Olesen [Tue, 2 Jul 2013 17:31:58 +0000 (17:31 +0000)]
Revert (most of) r185393 and r185395.

"Remove floating point computations form SpillPlacement.cpp."

These commits caused test failures in lencod on clang-native-arm-lnt.

I suspect these changes are only exposing an existing issue, but
reverting anyway to keep the bots passing while we investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185447 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Avoid unused variable warnings in Release builds.
Benjamin Kramer [Tue, 2 Jul 2013 17:24:00 +0000 (17:24 +0000)]
Hexagon: Avoid unused variable warnings in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix -Wsign-compare warning and remove windows-style line endings introduced by r185421
David Blaikie [Tue, 2 Jul 2013 16:48:10 +0000 (16:48 +0000)]
Fix -Wsign-compare warning and remove windows-style line endings introduced by r185421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185443 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[APFloat] Swap an early out check so we do not dereference str.end().
Michael Gottesman [Tue, 2 Jul 2013 15:50:05 +0000 (15:50 +0000)]
[APFloat] Swap an early out check so we do not dereference str.end().

Originally if D.firstSigDigit == str.end(), we will have already dereferenced
D.firstSigDigit in the first predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185437 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove address spaces from MC.
Rafael Espindola [Tue, 2 Jul 2013 15:49:13 +0000 (15:49 +0000)]
Remove address spaces from MC.

This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Use DSGFR over DSGR in more cases
Richard Sandiford [Tue, 2 Jul 2013 15:40:22 +0000 (15:40 +0000)]
[SystemZ] Use DSGFR over DSGR in more cases

Fixes some cases where we were using full 64-bit division for (sdiv i32, i32)
and (sdiv i64, i32).

The "32" in "SDIVREM32" just refers to the second operand.  The first operand
of all *DIVREM*s is a GR128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185435 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Use MVC to spill loads and stores
Richard Sandiford [Tue, 2 Jul 2013 15:28:56 +0000 (15:28 +0000)]
[SystemZ] Use MVC to spill loads and stores

Try to use MVC when spilling the destination of a simple load or the source
of a simple store.  As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet.  spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.

I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...

Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}.  It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Add the MVC instruction
Richard Sandiford [Tue, 2 Jul 2013 14:56:45 +0000 (14:56 +0000)]
[SystemZ] Add the MVC instruction

This is the first use of D(L,B) addressing, which required a fair bit
of surgery.  For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[XCore] Fix instruction selection for zext, mkmsk instructions.
Richard Osborne [Tue, 2 Jul 2013 14:46:34 +0000 (14:46 +0000)]
[XCore] Fix instruction selection for zext, mkmsk instructions.

r182680 replaced CountLeadingZeros_32 with a template function
countLeadingZeros that relies on using the correct argument type to give
the right result. The type passed in the XCore backend after this
revision was incorrect in a couple of places.

Patch by Robert Lytton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix ARM EHABI compact model 1 and 2 without handlerdata.
Logan Chien [Tue, 2 Jul 2013 12:43:27 +0000 (12:43 +0000)]
Fix ARM EHABI compact model 1 and 2 without handlerdata.

According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes.  The handler data consists of several words, and
should be terminated by zero.

In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager.
Elena Demikhovsky [Tue, 2 Jul 2013 12:24:22 +0000 (12:24 +0000)]
Fixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185421 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDAGCombiner: fix use-counting issue when forming zextload
Tim Northover [Tue, 2 Jul 2013 09:58:53 +0000 (09:58 +0000)]
DAGCombiner: fix use-counting issue when forming zextload

DAGCombiner was counting all uses of a load node  when considering whether it's
worth combining into a zextload. Really, it wants to ignore the chain and just
count real uses.

rdar://problem/13896307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185419 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with 'select...
Hal Finkel [Tue, 2 Jul 2013 05:21:11 +0000 (05:21 +0000)]
Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms)

I'm reverting this commit because:

 1. As discussed during review, it needs to be rewritten (to avoid creating and
then deleting instructions).

 2. This is causing optimizer crashes. Specifically, I'm seeing things like
this:

    While deleting: i1 %
    Use still stuck around after Def is destroyed:  <badref> = select i1 <badref>, i32 0, i32 1
    opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed.

   I'd guess that these will go away once we're no longer creating/deleting
instructions here, but just in case, I'm adding a regression test.

Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message:

InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms

Real world code sometimes has the denominator of a 'udiv' be a
'select'.  LLVM can handle such cases but only when the 'select'
operands are symmetric in structure (both select operands are a constant
power of two or a left shift, etc.).  This falls apart if we are dealt a
'udiv' where the code is not symetric or if the select operands lead us
to more select instructions.

Instead, we should treat the LHS and each select operand as a distinct
divide operation and try to optimize them independently.  If we can
to simplify each operation, then we can replace the 'udiv' with, say, a
'lshr' that has a new select with a bunch of new operands for the
select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185415 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd missing break statements. Noticed by inspection.
Nick Lewycky [Tue, 2 Jul 2013 05:02:56 +0000 (05:02 +0000)]
Add missing break statements. Noticed by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185414 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix typo in comment
Tobias Grosser [Tue, 2 Jul 2013 04:15:28 +0000 (04:15 +0000)]
Fix typo in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185413 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
Hal Finkel [Tue, 2 Jul 2013 03:39:34 +0000 (03:39 +0000)]
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling

There are a couple of (small) related changes here:

1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.

2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).

3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.

4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.

With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoIRVerifier: Correctly check attribute types
Tobias Grosser [Tue, 2 Jul 2013 03:28:10 +0000 (03:28 +0000)]
IRVerifier: Correctly check attribute types

Add missing parenthesis such that all and not only the very first attribute
is checked.

Testing this piece of code is not possible with an LLVM-IR test file, as the
LLVM-IR parser has a similar check such that the wrong IR does not even arrive
at the verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185408 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
Akira Hatanaka [Tue, 2 Jul 2013 00:00:02 +0000 (00:00 +0000)]
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.

No changes in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPR14728: DebugInfo: TLS variables with -gsplit-dwarf
David Blaikie [Mon, 1 Jul 2013 23:55:52 +0000 (23:55 +0000)]
PR14728: DebugInfo: TLS variables with -gsplit-dwarf

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185398 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[APFloat] Ensure that we can properly parse strings that do not have null terminators.
Michael Gottesman [Mon, 1 Jul 2013 23:54:08 +0000 (23:54 +0000)]
[APFloat] Ensure that we can properly parse strings that do not have null terminators.

rdar://14323230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185397 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix up some asserts that are within an if statement. This removes the need
Richard Trieu [Mon, 1 Jul 2013 23:42:53 +0000 (23:42 +0000)]
Fix up some asserts that are within an if statement.  This removes the need
for assert(0 && "text").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185396 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTweak some comments that referred to the old bias computations.
Jakob Stoklund Olesen [Mon, 1 Jul 2013 23:36:37 +0000 (23:36 +0000)]
Tweak some comments that referred to the old bias computations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185395 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Add support for TLS data relocations
Ulrich Weigand [Mon, 1 Jul 2013 23:33:29 +0000 (23:33 +0000)]
[PowerPC] Add support for TLS data relocations

This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove floating point computations form SpillPlacement.cpp.
Jakob Stoklund Olesen [Mon, 1 Jul 2013 23:19:39 +0000 (23:19 +0000)]
Remove floating point computations form SpillPlacement.cpp.

Patch by Benjamin Kramer!

Use the BlockFrequency class instead of floats in the Hopfield network
computations. This rescales the node Bias field from a [-2;2] float
range to two block frequencies BiasN and BiasP pulling in opposite
directions. This construct has a more predictable behavior when block
frequencies saturate.

The per-node scaling factors are no longer necessary, assuming the block
frequencies around a bundle are consistent.

This patch can cause the register allocator to make different spilling
decisions. The differences should be small.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185393 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChange if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
Richard Trieu [Mon, 1 Jul 2013 23:06:23 +0000 (23:06 +0000)]
Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Fix 32-bit PowerPC TLS relocs
Ulrich Weigand [Mon, 1 Jul 2013 22:27:57 +0000 (22:27 +0000)]
[PowerPC] Fix 32-bit PowerPC TLS relocs

Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
David Blaikie [Mon, 1 Jul 2013 21:45:25 +0000 (21:45 +0000)]
PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation

Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Support all condition register logical instructions
Ulrich Weigand [Mon, 1 Jul 2013 21:40:54 +0000 (21:40 +0000)]
[PowerPC] Support all condition register logical instructions

This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a newline.
Chad Rosier [Mon, 1 Jul 2013 21:31:10 +0000 (21:31 +0000)]
Add a newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDebug Info: clean up usage of Verify.
Manman Ren [Mon, 1 Jul 2013 21:02:01 +0000 (21:02 +0000)]
Debug Info: clean up usage of Verify.

No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185383 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoIndex: test/CodeGen/PowerPC/reloc-align.ll
Bill Schmidt [Mon, 1 Jul 2013 20:52:27 +0000 (20:52 +0000)]
Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll (revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll (revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
       OutStreamer.EmitRawText(StringRef("\tmsync"));
       return;
     }
+    break;
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA: {
+    // Verify alignment is legal, so we don't create relocations
+    // that can't be supported.
+    // FIXME:  This test is currently disabled for Darwin.  The test
+    // suite shows a handful of test cases that fail this check for
+    // Darwin.  Those need to be investigated before this sanity test
+    // can be enabled for those subtargets.
+    if (!Subtarget.isDarwin()) {
+      unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+      const MachineOperand &MO = MI->getOperand(OpNum);
+      if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+    }
+    // Now process the instruction normally.
+    break;
   }
+  }

   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
         SDLoc dl(GA);
         const GlobalValue *GV = GA->getGlobal();
+        // We can't perform this optimization for data whose alignment
+        // is insufficient for the instruction encoding.
+        if (GV->getAlignment() < 4 &&
+            (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+             StorageOpcode == PPC::LWA)) {
+          DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+          continue;
+        }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
Chad Rosier [Mon, 1 Jul 2013 20:49:23 +0000 (20:49 +0000)]
[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake PBQP require/preserve MachineLoopInfo - the spiller requires it.
Lang Hames [Mon, 1 Jul 2013 20:47:47 +0000 (20:47 +0000)]
Make PBQP require/preserve MachineLoopInfo - the spiller requires it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185378 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[docs] Amend confusing title
Sean Silva [Mon, 1 Jul 2013 20:45:12 +0000 (20:45 +0000)]
[docs] Amend confusing title

"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185377 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Reverse the order of source operands of shift and rotate instructions that
Akira Hatanaka [Mon, 1 Jul 2013 20:39:53 +0000 (20:39 +0000)]
[mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Also add "msync" alias
Ulrich Weigand [Mon, 1 Jul 2013 20:39:50 +0000 (20:39 +0000)]
[PowerPC] Also add "msync" alias

This adds an alias for "msync" (which is used on Book E
systems instead of "sync").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Increase the number of floating point control registers available to 32.
Akira Hatanaka [Mon, 1 Jul 2013 20:31:44 +0000 (20:31 +0000)]
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Fix test case to check that mips64 instructions are generated.
Akira Hatanaka [Mon, 1 Jul 2013 20:18:58 +0000 (20:18 +0000)]
[mips] Fix test case to check that mips64 instructions are generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185371 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReally fix the test. Sorry for the breakage...
Anton Korobeynikov [Mon, 1 Jul 2013 19:51:36 +0000 (19:51 +0000)]
Really fix the test. Sorry for the breakage...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185369 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the test which relies on uncommitted change
Anton Korobeynikov [Mon, 1 Jul 2013 19:50:31 +0000 (19:50 +0000)]
Fix the test which relies on uncommitted change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185368 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the build after r185363. Use llvm::next instead of raw next.
Cameron Zwarich [Mon, 1 Jul 2013 19:49:48 +0000 (19:49 +0000)]
Fix the build after r185363. Use llvm::next instead of raw next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185367 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd jump tables handling for MSP430.
Anton Korobeynikov [Mon, 1 Jul 2013 19:44:44 +0000 (19:44 +0000)]
Add jump tables handling for MSP430.
Patch by Job Noorman!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185364 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix PR16508.
Cameron Zwarich [Mon, 1 Jul 2013 19:42:46 +0000 (19:42 +0000)]
Fix PR16508.

When phis get lowered, destination copies are inserted using an iterator that is
determined once for all phis in the block, which BuildMI interprets as a request
to insert an instruction directly before the iterator. In the case of a cyclic
phi, source copies may also be inserted directly before this iterator, which can
cause source copies to be inserted before destination copies. The fix is to keep
an iterator to the last phi and then advance it while lowering each phi in order
to insert destination copies directly after the phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185363 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't form PPC CTR loops for over-sized exit counts
Hal Finkel [Mon, 1 Jul 2013 19:34:59 +0000 (19:34 +0000)]
Don't form PPC CTR loops for over-sized exit counts

Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: correct CodeGen of MOVZ/MOVK combinations.
Tim Northover [Mon, 1 Jul 2013 19:23:10 +0000 (19:23 +0000)]
AArch64: correct CodeGen of MOVZ/MOVK combinations.

According to the AArch64 ELF specification (4.6.8), it's the
assembler's responsibility to make sure the shift amount is correct in
relocated MOVZ/MOVK instructions.

This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF
(which happened to work out well for JIT tests). This commit should
make us compliant in this area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185360 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago(1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.
Matt Beaumont-Gay [Mon, 1 Jul 2013 18:58:53 +0000 (18:58 +0000)]
(1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.
(2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get
substituted by lit within the input filenames on the RUN line.
(3) XFAIL llvm-cov.test because it asserts:
include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185358 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Tim Northover [Mon, 1 Jul 2013 18:37:33 +0000 (18:37 +0000)]
Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")

Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDebug Info: Scope of a DebugLoc should not be null.
Manman Ren [Mon, 1 Jul 2013 18:20:30 +0000 (18:20 +0000)]
Debug Info: Scope of a DebugLoc should not be null.

No functionality change. Remove handling for the null case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185354 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Fix @got references to local symbols
Ulrich Weigand [Mon, 1 Jul 2013 18:19:56 +0000 (18:19 +0000)]
[PowerPC] Fix @got references to local symbols

A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.

Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Add "wait" instruction
Ulrich Weigand [Mon, 1 Jul 2013 17:21:23 +0000 (17:21 +0000)]
[PowerPC] Add "wait" instruction

This adds the "wait" instruction and its extended mnemonics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Support "eieio" instruction
Ulrich Weigand [Mon, 1 Jul 2013 17:06:26 +0000 (17:06 +0000)]
[PowerPC] Support "eieio" instruction

This adds support for the "eieio" instruction to
the asm parser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded c++ mode selector to head of SelectionDAGBuilder.h so editors open it in c...
Michael Gottesman [Mon, 1 Jul 2013 16:53:41 +0000 (16:53 +0000)]
Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it in c++ mode instead of c mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185348 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
Ulrich Weigand [Mon, 1 Jul 2013 16:52:55 +0000 (16:52 +0000)]
[PowerPC] Add some existing instructions to ppc64-encoding-bookII.s

The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end.  In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is.  This adds tests for those already supported
instructions / instruction forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185347 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Add variants of "sync" instruction
Ulrich Weigand [Mon, 1 Jul 2013 16:37:52 +0000 (16:37 +0000)]
[PowerPC] Add variants of "sync" instruction

This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoARM: relax the atomic release barrier to "dmb ishst"
Tim Northover [Mon, 1 Jul 2013 14:48:48 +0000 (14:48 +0000)]
ARM: relax the atomic release barrier to "dmb ishst"

I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Add support for module-scope inline asm
Justin Holewinski [Mon, 1 Jul 2013 13:00:14 +0000 (13:00 +0000)]
[NVPTX] Add support for module-scope inline asm

Since we were explicitly not calling AsmPrinter::doInitialization,
any module-scope inline asm was not being printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185336 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] We dont use NVBuiltin anymore
Justin Holewinski [Mon, 1 Jul 2013 12:59:08 +0000 (12:59 +0000)]
[NVPTX] We dont use NVBuiltin anymore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185335 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Cut down on physical register defs
Justin Holewinski [Mon, 1 Jul 2013 12:59:06 +0000 (12:59 +0000)]
[NVPTX] Cut down on physical register defs

We are using virtual registers throughout now, but we still need
to keep a few physical registers per class around to keep the
infrastructure happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185334 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] 64-bit ADDC/ADDE are not legal
Justin Holewinski [Mon, 1 Jul 2013 12:59:04 +0000 (12:59 +0000)]
[NVPTX] 64-bit ADDC/ADDE are not legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185333 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
Justin Holewinski [Mon, 1 Jul 2013 12:59:01 +0000 (12:59 +0000)]
[NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185332 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Handle signext/zeroext attributes properly
Justin Holewinski [Mon, 1 Jul 2013 12:58:58 +0000 (12:58 +0000)]
[NVPTX] Handle signext/zeroext attributes properly

Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185331 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Add support for native SIGN_EXTEND_INREG where available
Justin Holewinski [Mon, 1 Jul 2013 12:58:56 +0000 (12:58 +0000)]
[NVPTX] Add support for native SIGN_EXTEND_INREG where available

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185330 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
Justin Holewinski [Mon, 1 Jul 2013 12:58:52 +0000 (12:58 +0000)]
[NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185329 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value
Justin Holewinski [Mon, 1 Jul 2013 12:58:48 +0000 (12:58 +0000)]
[NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185328 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agollvm-symbolizer: Recognize a drive letter on win32. Then "REQUIRES: shell" can be...
NAKAMURA Takumi [Mon, 1 Jul 2013 09:51:42 +0000 (09:51 +0000)]
llvm-symbolizer: Recognize a drive letter on win32. Then "REQUIRES: shell" can be removed.

FIXME: Could we use llvm::sys::Path here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185322 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded the test missed from r185080.
Serge Pavlov [Mon, 1 Jul 2013 09:02:33 +0000 (09:02 +0000)]
Added the test missed from r185080.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185316 91177308-0d34-0410-b5e6-96231b3b80d8