Start implementing MachineCodeEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4870 91177308-0d34-0410-b5e6-96231b3b80d8

Start adding to the meat of MachineCodeEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4869 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate OtherFrm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4868 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comment
Remove handling of OtherFrm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4867 91177308-0d34-0410-b5e6-96231b3b80d8

Initial support for machine code emission

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4866 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial support for machine code emission

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4865 91177308-0d34-0410-b5e6-96231b3b80d8

Initial version of MachineCodeEmitter interface: empty

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4864 91177308-0d34-0410-b5e6-96231b3b80d8

The hopefully final version of addPassesToEmitMachineCode which does not
have any question about ownership

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4863 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore generated files gram.tab.c and gram.tab.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4862 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore generated files Lexer.cpp and llvmAsmParser.*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4861 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore generated files FileLexer.* and FileParser.*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4860 91177308-0d34-0410-b5e6-96231b3b80d8

Add comment about ownership semantics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4859 91177308-0d34-0410-b5e6-96231b3b80d8

* Abstracted out stack space allocation into its own function
* Added saving of register values to the stack

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4858 91177308-0d34-0410-b5e6-96231b3b80d8

Fix order of operands on a store from reg to [reg+offset].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4857 91177308-0d34-0410-b5e6-96231b3b80d8

Add stub to emit machine code for JIT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4856 91177308-0d34-0410-b5e6-96231b3b80d8

Continued support for field intitializers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4855 91177308-0d34-0410-b5e6-96231b3b80d8

Continued support for field initializer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4854 91177308-0d34-0410-b5e6-96231b3b80d8

Continued support for Field Initializer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4853 91177308-0d34-0410-b5e6-96231b3b80d8

Adjustments due to new FieldInit stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4852 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments, factor out common code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4851 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for field exprs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4850 91177308-0d34-0410-b5e6-96231b3b80d8

* Move BitsInit::resolveReferences up with the rest of BitsInit code
* Initial support for field expressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4849 91177308-0d34-0410-b5e6-96231b3b80d8

Initial support for Field Expressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4848 91177308-0d34-0410-b5e6-96231b3b80d8

Add correct dependency

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4847 91177308-0d34-0410-b5e6-96231b3b80d8

Split up targets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4846 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4845 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to build lib/Support before the utilities, then use the new
makefile in utils to build the utilities

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4844 91177308-0d34-0410-b5e6-96231b3b80d8

Initial checkin of TableGen utility

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4843 91177308-0d34-0410-b5e6-96231b3b80d8

Add makefile to build subdirs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4842 91177308-0d34-0410-b5e6-96231b3b80d8

Add rawfrm flags

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4841 91177308-0d34-0410-b5e6-96231b3b80d8

Don't add implicit regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4840 91177308-0d34-0410-b5e6-96231b3b80d8

brg

InstSelectSimple.cpp: Refactor out conversion of byte, short -> int
  from visitReturnInst() to new method, promote32().
 Use it in both visitReturnInst() and visitCallInst().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4839 91177308-0d34-0410-b5e6-96231b3b80d8

brg

InstSelectSimple.cpp: First draft of visitCallInst method, handling
 int/float args.
X86InstrInfo.def: Add entries for CALL with 32-bit pc relative arg, and
 PUSH with 32-bit reg arg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4838 91177308-0d34-0410-b5e6-96231b3b80d8

Several fixes:
(1) Applied patch from Casey to implement iterator::operator= correctly:
    it should use a pointer, not a reference.
(2) Added operators == and !=, and method all().
(3) Important bug fix: excess bits need to be ignored in operations
    like ==, count(), and all().  We do this by ensuring excess bits
    in the last bitset are always 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4837 91177308-0d34-0410-b5e6-96231b3b80d8

Fix logical error in TD pass: we should clear Mod/Ref bits of each caller
before inlining their graphs into a function.  To support this,
added flags to CloneFlags to strip/keep Mod/Ref bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4836 91177308-0d34-0410-b5e6-96231b3b80d8

Added flags to CloneFlags to strip/keep Mod/Ref bits when cloning a graph.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4835 91177308-0d34-0410-b5e6-96231b3b80d8

No longer need local graph to find call sites.
Also some major fixes within IPModRef.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4834 91177308-0d34-0410-b5e6-96231b3b80d8

(1) Bug fix that was causing nodes with dangling references to be freed.
    We run removeDeadNodes() on the TD graph up front before using it.
(2) Major enhancement to printing of results: now we list the actual objects
    that are mod/ref instead of just printing the bit vectors.
Also an important bug fix in TDDataStructures pass (no change here):
clear Mod/Ref bits of callers before inlining into a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4833 91177308-0d34-0410-b5e6-96231b3b80d8

brg

InstSelectSimple.cpp: Add some comments that say what I'm going to do for
 calls and casts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4832 91177308-0d34-0410-b5e6-96231b3b80d8

Keep global nodes in each DS Graph (by forcing them to be marked live).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4831 91177308-0d34-0410-b5e6-96231b3b80d8

Oops. Got the MOVrm and MOVmr mixed up. Fixed. We can now print out
instructions correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4830 91177308-0d34-0410-b5e6-96231b3b80d8

Enable the register allocator pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4829 91177308-0d34-0410-b5e6-96231b3b80d8

A simple (spilling) register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4828 91177308-0d34-0410-b5e6-96231b3b80d8

Added methods to read/write values to stack in .h, fixed implementation in
.cpp to return the iterator correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4827 91177308-0d34-0410-b5e6-96231b3b80d8

Added -*- C++ -*- mode to the comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4826 91177308-0d34-0410-b5e6-96231b3b80d8

Add a simple way to add memory locations of format [reg+offset]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4825 91177308-0d34-0410-b5e6-96231b3b80d8

Added virtual functions for storing and retrieving values from the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4824 91177308-0d34-0410-b5e6-96231b3b80d8

Instead of checking op.getType() against MO_VirtualRegister and
MO_MachineRegister, we no longer distinguish Virtual vs. Machine registers
externally, they're ALL registers, all equal.

Registers are only differentiated whether they are >=
MRegisterInfo::FirstVirtual or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4823 91177308-0d34-0410-b5e6-96231b3b80d8

Set SSARegMap to NULL after deleting it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4822 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/InstSelectSimple.cpp: Add visitCallInst, visitCastInst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4821 91177308-0d34-0410-b5e6-96231b3b80d8

Make testcase more interesting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4820 91177308-0d34-0410-b5e6-96231b3b80d8

Handle cmp Reg, 0 correctly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4819 91177308-0d34-0410-b5e6-96231b3b80d8

Printing support for more stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4818 91177308-0d34-0410-b5e6-96231b3b80d8

Don't add implicit operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4817 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off by one bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4816 91177308-0d34-0410-b5e6-96231b3b80d8

Add fixme

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4815 91177308-0d34-0410-b5e6-96231b3b80d8

Minor code cleanups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4814 91177308-0d34-0410-b5e6-96231b3b80d8

Implement printing of store instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4813 91177308-0d34-0410-b5e6-96231b3b80d8

The big change here is to handle printing/emission of X86II::MRMSrcMem
instructions.  Right now the only users are load instructions, and Misha's
spill code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4812 91177308-0d34-0410-b5e6-96231b3b80d8

Remove implicit information from instruction selector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4811 91177308-0d34-0410-b5e6-96231b3b80d8

Add printing information for MUL and DIV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4810 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug that prevented compilation of multiple functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4809 91177308-0d34-0410-b5e6-96231b3b80d8

Move test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4808 91177308-0d34-0410-b5e6-96231b3b80d8

Shuffle testcases around

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4807 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4806 91177308-0d34-0410-b5e6-96231b3b80d8

Remove opcode information for instructions that are completely defined now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4805 91177308-0d34-0410-b5e6-96231b3b80d8

Add printing support for sahf & setcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4804 91177308-0d34-0410-b5e6-96231b3b80d8

Add printing support for /0 /1 type instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4803 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for /0 /1, etc type instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4802 91177308-0d34-0410-b5e6-96231b3b80d8

User defined operators are not supposed to live beyond the lifetime of the
pass.  Detect and flag them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4801 91177308-0d34-0410-b5e6-96231b3b80d8

Rename the SetCC X86 instructions to reflect the fact that they are the
register versions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4800 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify setcc code a bit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4799 91177308-0d34-0410-b5e6-96231b3b80d8

Support Registers of the form (B8+ rd) for example

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4798 91177308-0d34-0410-b5e6-96231b3b80d8

Dont' set flags

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4797 91177308-0d34-0410-b5e6-96231b3b80d8

Implement printing more, implement opcode output more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4796 91177308-0d34-0410-b5e6-96231b3b80d8

Huge diff do to reindeinting comments.
Basically just adds OpSize flags for instructions that need them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4795 91177308-0d34-0410-b5e6-96231b3b80d8

Add new prefix flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4794 91177308-0d34-0410-b5e6-96231b3b80d8

Print another class of instructions correctly, giving us: xorl EDX, EDX
for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4793 91177308-0d34-0410-b5e6-96231b3b80d8

Booleans are types too. And they get stored in bytes. And InstructionSelection
doesn't assert fail. And everyone's happy. Yay!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4792 91177308-0d34-0410-b5e6-96231b3b80d8

Checkin testcases for bugpoint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4791 91177308-0d34-0410-b5e6-96231b3b80d8

Build bugpoint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4790 91177308-0d34-0410-b5e6-96231b3b80d8

Initial checkin of bugpoint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4789 91177308-0d34-0410-b5e6-96231b3b80d8

Initial checkin of Module cloning support stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4788 91177308-0d34-0410-b5e6-96231b3b80d8

Cloning stuff doesn't modify the source module

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4787 91177308-0d34-0410-b5e6-96231b3b80d8

X86 target builds fine now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4786 91177308-0d34-0410-b5e6-96231b3b80d8

Fix symbol table problem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4785 91177308-0d34-0410-b5e6-96231b3b80d8

Add definitions for function headers from MRegisterInfo.h:
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4784 91177308-0d34-0410-b5e6-96231b3b80d8

Check not only for MO_VirtualRegister, but MO_MachineRegister as well when
printing out assembly. After all, we want the real thing too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4783 91177308-0d34-0410-b5e6-96231b3b80d8

Initialize the SSARegMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4782 91177308-0d34-0410-b5e6-96231b3b80d8

MRegisterInfo.h - Added prototypes for functions we need to map a register to
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8

Don't build X86 target yet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4780 91177308-0d34-0410-b5e6-96231b3b80d8

  - Eliminated the deferred symbol table stuff in Module & Function, it really
    wasn't an optimization and it was causing lots of bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4779 91177308-0d34-0410-b5e6-96231b3b80d8

Fix minor bugs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4778 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate the concept of a deferred symbol table.  The optimization really isn't,
and it causes obscure bugs to show up in passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4777 91177308-0d34-0410-b5e6-96231b3b80d8

Add mapping in MachineFunction from SSA regs to Register Classes. Also,
uncovered a bug where registers were not being put in a map if they were not
found...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4776 91177308-0d34-0410-b5e6-96231b3b80d8

Sigh. Fixed some speling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4775 91177308-0d34-0410-b5e6-96231b3b80d8

SSARegMap -- the mapping between SSARegisters and their RegisterClasses, which
imply types of SSA Registers. This is on a per-function basis, so the
MachineFunction contains the SSARegMap, and has accessor functions to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4774 91177308-0d34-0410-b5e6-96231b3b80d8

Thanks to the R8, R16, and R32 macros, I can now deal with registers that
belong to different register classes easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4773 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unneccesary #include

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4772 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the CloneFunction function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4771 91177308-0d34-0410-b5e6-96231b3b80d8