oota-llvm.git
10 years agoFix uninitialized warning in llvm/lib/IR/DataLayout.cpp.
Cameron McInally [Mon, 13 Jan 2014 22:04:55 +0000 (22:04 +0000)]
Fix uninitialized warning in llvm/lib/IR/DataLayout.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199147 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[DAG] Refactor ReassociateOps - no functional change intended.
Juergen Ributzka [Mon, 13 Jan 2014 21:49:25 +0000 (21:49 +0000)]
[DAG] Refactor ReassociateOps - no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199146 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a check that the host compiler is modern to CMake, take 1. This is
Chandler Carruth [Mon, 13 Jan 2014 21:47:35 +0000 (21:47 +0000)]
Add a check that the host compiler is modern to CMake, take 1. This is
likely to be reverted and re-applied a few times. The minimum versions
we're aiming at:

  GCC 4.7
  Clang 3.1
  MSVC 17.0 (Visual Studio 2012)

Let me know if something breaks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199145 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[DAG] Teach DAG to also reassociate vector operations
Juergen Ributzka [Mon, 13 Jan 2014 20:51:35 +0000 (20:51 +0000)]
[DAG] Teach DAG to also reassociate vector operations

This commit teaches DAG to reassociate vector ops, which in turn enables
constant folding of vector op chains that appear later on during custom lowering
and DAG combine.

Reviewed by Andrea Di Biagio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199135 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoHide the pre-RA-sched= option.
Andrew Trick [Mon, 13 Jan 2014 20:08:27 +0000 (20:08 +0000)]
Hide the pre-RA-sched= option.

This is a very confusing option for a feature that will go away.

-enable-misched is exposed instead to help triage issues with the new
scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199133 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks
Weiming Zhao [Mon, 13 Jan 2014 18:47:54 +0000 (18:47 +0000)]
Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks

The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdate getLazyBitcodeModule to use ErrorOr for error handling.
Rafael Espindola [Mon, 13 Jan 2014 18:31:04 +0000 (18:31 +0000)]
Update getLazyBitcodeModule to use ErrorOr for error handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199125 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
Andrea Di Biagio [Mon, 13 Jan 2014 16:51:00 +0000 (16:51 +0000)]
[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.

APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix indentation.
Joerg Sonnenberger [Mon, 13 Jan 2014 15:50:36 +0000 (15:50 +0000)]
Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199118 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SystemZ] Flesh out stackrestore test (frame-11.ll)
Richard Sandiford [Mon, 13 Jan 2014 15:44:44 +0000 (15:44 +0000)]
[SystemZ] Flesh out stackrestore test (frame-11.ll)

...so that it does something vaguely sensible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199117 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SystemZ] Add "volatile" to a dead store in variable-loc.ll
Richard Sandiford [Mon, 13 Jan 2014 15:42:16 +0000 (15:42 +0000)]
[SystemZ] Add "volatile" to a dead store in variable-loc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199116 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SystemZ] Improve risbg-01.ll test
Richard Sandiford [Mon, 13 Jan 2014 15:40:25 +0000 (15:40 +0000)]
[SystemZ] Improve risbg-01.ll test

The old mask in f24 wasn't well chosen because the lshr would always be zero.
CodeGen didn't detect this but InstCombine would.  The new mask ensures
that both shifts are needed.

f26 is specifically testing for a wrap-around mask.  The AND can be applied
to just the shift left, either before or after the shift.  Again, CodeGen
kept it in the original form but InstCombine would mask after the shift
instead.  The exact choice of NILF isn't important for the test so I just
dropped it and kept the rotate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199115 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SystemZ] Optimize (sext (ashr (shl ...), ...))
Richard Sandiford [Mon, 13 Jan 2014 15:17:53 +0000 (15:17 +0000)]
[SystemZ] Optimize (sext (ashr (shl ...), ...))

...into (ashr (shl (anyext X), ...), ...), which requires one fewer
instruction.  The (anyext X) can sometimes be simplified too.

I didn't do this in DAGCombiner because widening shifts isn't a win
on all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agofix a -Wdocumentation warning.
Chris Lattner [Mon, 13 Jan 2014 15:10:11 +0000 (15:10 +0000)]
fix a -Wdocumentation warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199113 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: add test for r199108. Oops.
Tim Northover [Mon, 13 Jan 2014 14:20:25 +0000 (14:20 +0000)]
ARM: add test for r199108. Oops.

rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199109 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.
Tim Northover [Mon, 13 Jan 2014 14:19:17 +0000 (14:19 +0000)]
ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.

Previously we only used GPR for the destination placeholder in "ldr rD, [pc,
incorrect codegen under the integrated assembler.

This should fix both issues (which probably only affect MachO targets at the
moment).

rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199108 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[x86] Fix retq/retl handling in 64-bit mode
David Woodhouse [Mon, 13 Jan 2014 14:05:59 +0000 (14:05 +0000)]
[x86] Fix retq/retl handling in 64-bit mode

This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Split DominatorTree into a concrete analysis result object which
Chandler Carruth [Mon, 13 Jan 2014 13:07:17 +0000 (13:07 +0000)]
[PM] Split DominatorTree into a concrete analysis result object which
can be used by both the new pass manager and the old.

This removes it from any of the virtual mess of the pass interfaces and
lets it derive cleanly from the DominatorTreeBase<> template. In turn,
tons of boilerplate interface can be nuked and it turns into a very
straightforward extension of the base DominatorTree interface.

The old analysis pass is now a simple wrapper. The names and style of
this split should match the split between CallGraph and
CallGraphWrapperPass. All of the users of DominatorTree have been
updated to match using many of the same tricks as with CallGraph. The
goal is that the common type remains the resulting DominatorTree rather
than the pass. This will make subsequent work toward the new pass
manager significantly easier.

Also in numerous places things became cleaner because I switched from
re-running the pass (!!! mid way through some other passes run!!!) to
directly recomputing the domtree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199104 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM][cleanup] Clean up comments and use modern doxygen in this file.
Chandler Carruth [Mon, 13 Jan 2014 13:06:58 +0000 (13:06 +0000)]
[PM][cleanup] Clean up comments and use modern doxygen in this file.
This is a precursor to breaking the pass that computes the DominatorTree
apart from the concrete DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199103 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAVX-512: Embedded Rounding Control - encoding and printing
Elena Demikhovsky [Mon, 13 Jan 2014 12:55:03 +0000 (12:55 +0000)]
AVX-512: Embedded Rounding Control - encoding and printing
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Fix the const-correctness of the generic DominatorTreeBase to
Chandler Carruth [Mon, 13 Jan 2014 11:58:34 +0000 (11:58 +0000)]
[PM] Fix the const-correctness of the generic DominatorTreeBase to
support notionally const queries even though they may trigger DFS
numbering updates.

The updating of DFS numbers and tracking of slow queries do not mutate
the observable state of the domtree. They should be const to
differentiate them from the APIs which mutate the tree directly to do
incremental updates.

This will make it possible in a world where the DominatorTree is not
a pass but merely the result of running a pass to derive DominatorTree
from the base class as it was originally designed, removing a huge
duplication of API in DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199101 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Pull the generic graph algorithms and data structures for dominator
Chandler Carruth [Mon, 13 Jan 2014 10:52:56 +0000 (10:52 +0000)]
[PM] Pull the generic graph algorithms and data structures for dominator
trees into the Support library.

These are all expressed in terms of the generic GraphTraits and CFG,
with no reliance on any concrete IR types. Putting them in support
clarifies that and makes the fact that the static analyzer in Clang uses
them much more sane. When moving the Dominators.h file into the IR
library I claimed that this was the right home for it but not something
I planned to work on. Oops.

So why am I doing this? It happens to be one step toward breaking the
requirement that IR verification can only be performed from inside of
a pass context, which completely blocks the implementation of
verification for the new pass manager infrastructure. Fixing it will
also allow removing the concept of the "preverify" step (WTF???) and
allow the verifier to cleanly flag functions which fail verification in
a way that precludes even computing dominance information. Currently,
that results in a fatal error even when you ask the verifier to not
fatally error. It's awesome like that.

The yak shaving will continue...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199095 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "ReMat: fix overly cavalier attitude to sub-register indices"
Tim Northover [Mon, 13 Jan 2014 10:49:11 +0000 (10:49 +0000)]
Revert "ReMat: fix overly cavalier attitude to sub-register indices"

Very sorry, this was a premature patch that I still need to investigate and
finish off (for some reason beyond me at the moment it doesn't actually fix the
issue in all cases).

This reverts commit r199091.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199093 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDocs: fix sign of division and increase equivocation on code generated.
Tim Northover [Mon, 13 Jan 2014 10:47:04 +0000 (10:47 +0000)]
Docs: fix sign of division and increase equivocation on code generated.

I should have been a politician.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199092 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReMat: fix overly cavalier attitude to sub-register indices
Tim Northover [Mon, 13 Jan 2014 10:47:01 +0000 (10:47 +0000)]
ReMat: fix overly cavalier attitude to sub-register indices

There are two attempted optimisations in reMaterializeTrivialDef, trying to
avoid promoting the size of a register too much when rematerializing.
Unfortunately, both appear to be flawed. First, we see if the original register
would have worked, but this is inadequate. Consider:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0 = COPY v1:Q1 (v1, v2 are QQ)
    ...
    uses of v2

In this case even though v2 *could* be used directly as the output of
SOMETHING, this would set the wrong bits of the QQ register involved. The
correct rematerialization must be:

    v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ)
    ...
    uses of v2:Q1_Q2

For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then
we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try
to hunt for a class between v1 and v2 that works. Unfortunately, this is also
wrong:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ)
    ...
    uses of v2 as a QQQ

The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current
logic would decide that v2 could be a QQ (no interest is taken in later uses).

This patch, therefore, always accepts the widened register class without trying
to be clever. Generally there is no penalty to this (e.g. in the common GR32 <
GR64 case, expanding the width doesn't matter because it's not like you were
going to do anything else with the high bits of a GR32 register). It can
increase register pressure in cases like the ARM VFP regs though (multiple
non-overlapping but equivalent subregisters). Hopefully this situation is rare
enough that it won't matter.

Unfortunately, no in-tree targets actually expose this as far as I can tell
(there are so few isAsCheapAsAMove instructions for it to trigger on) so I've
been unable to produce a test. It was exposed in our ARM64 SPEC tests though,
and I will be adding a test there that we should be able to contribute
soon(TM).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199091 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[cleanup] Re-sort the examples #include lines with my sort_includes
Chandler Carruth [Mon, 13 Jan 2014 09:58:03 +0000 (09:58 +0000)]
[cleanup] Re-sort the examples #include lines with my sort_includes
script.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199089 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[cleanup] Fix the includes in the examples for r199082.
Chandler Carruth [Mon, 13 Jan 2014 09:53:45 +0000 (09:53 +0000)]
[cleanup] Fix the includes in the examples for r199082.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199087 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[cleanup] Switch comments to use '\brief' style instead of '@brief'
Chandler Carruth [Mon, 13 Jan 2014 09:31:09 +0000 (09:31 +0000)]
[cleanup] Switch comments to use '\brief' style instead of '@brief'
style, and remove some unnecessary comments (the code is perfectly
self-documenting here). Also clang-format the function declarations as
they wrap cleanly now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199084 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[cleanup] Move the Dominators.h and Verifier.h headers into the IR
Chandler Carruth [Mon, 13 Jan 2014 09:26:24 +0000 (09:26 +0000)]
[cleanup] Move the Dominators.h and Verifier.h headers into the IR
directory. These passes are already defined in the IR library, and it
doesn't make any sense to have the headers in Analysis.

Long term, I think there is going to be a much better way to divide
these matters. The dominators code should be fully separated into the
abstract graph algorithm and have that put in Support where it becomes
obvious that evn Clang's CFGBlock's can use it. Then the verifier can
manually construct dominance information from the Support-driven
interface while the Analysis library can provide a pass which both
caches, reconstructs, and supports a nice update API.

But those are very long term, and so I don't want to leave the really
confusing structure until that day arrives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199082 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[cleanup] Add a missing include exposed by resorting other includes.
Chandler Carruth [Mon, 13 Jan 2014 08:09:47 +0000 (08:09 +0000)]
[cleanup] Add a missing include exposed by resorting other includes.
Should fix the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199081 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRe-sort #include lines again, prior to moving headers around.
Chandler Carruth [Mon, 13 Jan 2014 08:04:33 +0000 (08:04 +0000)]
Re-sort #include lines again, prior to moving headers around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199080 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Wire up support for writing bitcode with new PM.
Chandler Carruth [Mon, 13 Jan 2014 07:38:24 +0000 (07:38 +0000)]
[PM] Wire up support for writing bitcode with new PM.

This moves the old pass creation functionality to its own header and
updates the callers of that routine. Then it adds a new PM supporting
bitcode writer to the header file, and wires that up in the opt tool.
A test is added that round-trips code into bitcode and back out using
the new pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199078 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and mkdir(1...
NAKAMURA Takumi [Mon, 13 Jan 2014 05:55:10 +0000 (05:55 +0000)]
llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and mkdir(1) at the top.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199077 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[CMake] Move BUG_REPORT_URL from clang to llvm.
NAKAMURA Takumi [Mon, 13 Jan 2014 05:25:13 +0000 (05:25 +0000)]
[CMake] Move BUG_REPORT_URL from clang to llvm.

It was too late to set BUG_REPORT_URL after configure_file(config.h).
BUG_REPORT_URL in config.h.cmake would be updated at 2nd run of cmake.
It caused many recompilations.

FYI, configure handles BUG_REPORT_URL in llvm side.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199076 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Wire up support for printing assembly output from the opt command.
Chandler Carruth [Mon, 13 Jan 2014 05:16:45 +0000 (05:16 +0000)]
[PM] Wire up support for printing assembly output from the opt command.
This lets us round-trip IR in the expected manner with the opt tool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199075 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Add an enum for describing the desired output strategy, and run
Chandler Carruth [Mon, 13 Jan 2014 03:08:40 +0000 (03:08 +0000)]
[PM] Add an enum for describing the desired output strategy, and run
that through the interface rather than a simple bool. This should allow
starting to wire up real output to round-trip IR through opt with the
new pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199071 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64 NEON] Add missing patterns for bitcast from or to v1f64
Kevin Qin [Mon, 13 Jan 2014 01:58:38 +0000 (01:58 +0000)]
[AArch64 NEON] Add missing patterns for bitcast from or to v1f64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector
Kevin Qin [Mon, 13 Jan 2014 01:56:29 +0000 (01:56 +0000)]
[AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector

This patch covered 2 more scenarios:

1.  Two operands of shuffle_vector are the same, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

2. One of operands is undef, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

After this patch, perm instructions will have chance to be emitted instead of lots of INS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199069 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agocorrect target directive handling error handling
Saleem Abdulrasool [Mon, 13 Jan 2014 01:15:39 +0000 (01:15 +0000)]
correct target directive handling error handling

The target specific parser should return `false' if the target AsmParser handles
the directive, and `true' if the generic parser should handle the directive.
Many of the target specific directive handlers would `return Error' which does
not follow these semantics.  This change simply changes the target specific
routines to conform to the semantis of the ParseDirective correctly.

Conformance to the semantics improves diagnostics emitted for the invalid
directives.  X86 is taken as a sample to ensure that multiple diagnostics are
not presented for a single error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199068 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoHandle bundled terminators in isBlockOnlyReachableByFallthrough.
Jakob Stoklund Olesen [Sun, 12 Jan 2014 19:24:08 +0000 (19:24 +0000)]
Handle bundled terminators in isBlockOnlyReachableByFallthrough.

Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.

Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199061 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[CMake] Add a comment to tablegen's copy_if_different. Ninja reports every action...
NAKAMURA Takumi [Sun, 12 Jan 2014 17:42:43 +0000 (17:42 +0000)]
[CMake] Add a comment to tablegen's copy_if_different. Ninja reports every action by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199058 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoraw_fd_ostream: Don't change STDERR to O_BINARY, or w*printf() (in assert()) would...
NAKAMURA Takumi [Sun, 12 Jan 2014 16:14:24 +0000 (16:14 +0000)]
raw_fd_ostream: Don't change STDERR to O_BINARY, or w*printf() (in assert()) would barf wide chars after llvm::errs().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199057 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake test independent of scheduling
Nico Rieck [Sun, 12 Jan 2014 15:57:38 +0000 (15:57 +0000)]
Make test independent of scheduling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199055 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoraw_stream formatter: [Win32] Use std::signbit() if available, instead of _fpclass().
NAKAMURA Takumi [Sun, 12 Jan 2014 14:44:46 +0000 (14:44 +0000)]
raw_stream formatter: [Win32] Use std::signbit() if available, instead of _fpclass().

FIXME: It should be generic to C++11. For now, it is dedicated to mingw-w64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199052 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/CodeGen/X86/shl_undef.ll: Tweak to satisfy r199050.
NAKAMURA Takumi [Sun, 12 Jan 2014 14:41:41 +0000 (14:41 +0000)]
llvm/test/CodeGen/X86/shl_undef.ll: Tweak to satisfy r199050.

Use intel syntax, or "shl" might hit "pushl".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199051 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix non-deterministic SDNodeOrder-dependent codegen
Nico Rieck [Sun, 12 Jan 2014 14:09:17 +0000 (14:09 +0000)]
Fix non-deterministic SDNodeOrder-dependent codegen

Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code
generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Add module and function printing passes for the new pass manager.
Chandler Carruth [Sun, 12 Jan 2014 12:15:39 +0000 (12:15 +0000)]
[PM] Add module and function printing passes for the new pass manager.

This implements the legacy passes in terms of the new ones. It adds
basic testing using explicit runs of the passes. Next up will be wiring
the basic output mechanism of opt up when the new pass manager is
engaged unless bitcode writing is requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199049 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Revert an accidental commit of total BS code. This was halfway
Chandler Carruth [Sun, 12 Jan 2014 11:41:43 +0000 (11:41 +0000)]
[PM] Revert an accidental commit of total BS code. This was halfway
through being editted, and I forgot to delete it before committing.
What's more awesome is that it compiles cleanly!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199048 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Simplify the IR printing passes significantly now that a narrower
Chandler Carruth [Sun, 12 Jan 2014 11:40:03 +0000 (11:40 +0000)]
[PM] Simplify the IR printing passes significantly now that a narrower
API is exposed.

This removes the support for deleting the ostream, switches the member
and constructor order arround to be consistent with the creation
routines, and switches to using references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199047 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Update one user of the printing pass API that I missed.
Chandler Carruth [Sun, 12 Jan 2014 11:39:04 +0000 (11:39 +0000)]
[PM] Update one user of the printing pass API that I missed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199046 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Simplify the interface exposed for IR printing passes.
Chandler Carruth [Sun, 12 Jan 2014 11:30:46 +0000 (11:30 +0000)]
[PM] Simplify the interface exposed for IR printing passes.

Nothing was using the ability of the pass to delete the raw_ostream it
printed to, and nothing was trying to pass it a pointer to the
raw_ostream. Also, the function variant had a different order of
arguments from all of the others which was just really confusing. Now
the interface accepts a reference, doesn't offer to delete it, and uses
a consistent order. The implementation of the printing passes haven't
been updated with this simplification, this is just the API switch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199044 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Run clang-format and remove redundant or obvious comments before
Chandler Carruth [Sun, 12 Jan 2014 11:16:01 +0000 (11:16 +0000)]
[PM] Run clang-format and remove redundant or obvious comments before
the heavy factoring needed to share logic between the new pass manager
and the old.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199043 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Rename the IR printing pass header to a more generic and correct
Chandler Carruth [Sun, 12 Jan 2014 11:10:32 +0000 (11:10 +0000)]
[PM] Rename the IR printing pass header to a more generic and correct
name to match the source file which I got earlier. Update the include
sites. Also modernize the comments in the header to use the more
recommended doxygen style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199041 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Un-indent this file-level namespace. It's far more common to not
Chandler Carruth [Sun, 12 Jan 2014 10:56:57 +0000 (10:56 +0000)]
[PM] Un-indent this file-level namespace. It's far more common to not
indent the outer-most llvm namespace in header files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199040 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Fix a bunch of bugs I spotted by inspection when working on this
Chandler Carruth [Sun, 12 Jan 2014 10:02:02 +0000 (10:02 +0000)]
[PM] Fix a bunch of bugs I spotted by inspection when working on this
code. Copious tests added to cover these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199039 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Add support for parsing function passes and function pass manager
Chandler Carruth [Sun, 12 Jan 2014 09:34:22 +0000 (09:34 +0000)]
[PM] Add support for parsing function passes and function pass manager
nests to the opt commandline support. This also showcases the
implicit-initial-manager support which will be most useful for testing.
There are several bugs that I spotted by inspection here that I'll fix
with test cases in subsequent commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199038 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM IAS: fix diagnostics of improper qualification
Saleem Abdulrasool [Sun, 12 Jan 2014 05:25:44 +0000 (05:25 +0000)]
ARM IAS: fix diagnostics of improper qualification

An improper qualifier would result in a superfluous error due to the parser not
consuming the remainder of the statement.  Simply consume the remainder of the
statement to avoid the error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199035 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[Sparc] Add support for parsing floating point instructions.
Venkatraman Govindaraju [Sun, 12 Jan 2014 04:48:54 +0000 (04:48 +0000)]
[Sparc] Add support for parsing floating point instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
Saleem Abdulrasool [Sun, 12 Jan 2014 04:36:01 +0000 (04:36 +0000)]
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions

The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.
Venkatraman Govindaraju [Sun, 12 Jan 2014 04:34:31 +0000 (04:34 +0000)]
[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199031 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoThe SPARCv9 ABI returns a float in %f0.
Jakob Stoklund Olesen [Sun, 12 Jan 2014 04:13:17 +0000 (04:13 +0000)]
The SPARCv9 ABI returns a float in %f0.

This is different from the argument passing convention which puts the
first float argument in %f1.

With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...

Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199028 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTypo
Joerg Sonnenberger [Sun, 12 Jan 2014 03:38:30 +0000 (03:38 +0000)]
Typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199027 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd missing mul aliases for armv4 support. Add checks that armv4 can
Joerg Sonnenberger [Sun, 12 Jan 2014 03:35:18 +0000 (03:35 +0000)]
Add missing mul aliases for armv4 support. Add checks that armv4 can
assemble the various mul instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199026 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSwitch-to-lookup tables: Don't require a result for the default
Hans Wennborg [Sun, 12 Jan 2014 00:44:41 +0000 (00:44 +0000)]
Switch-to-lookup tables: Don't require a result for the default
case when the lookup table doesn't have any holes.

This means we can build a lookup table for switches like this:

  switch (x) {
    case 0: return 1;
    case 1: return 2;
    case 2: return 3;
    case 3: return 4;
    default: exit(1);
  }

The default case doesn't yield a constant result here, but that doesn't matter,
since a default result is only necessary for filling holes in the lookup table,
and this table doesn't have any holes.

This makes us transform 505 more switches in a clang bootstrap, and shaves 164 KB
off the resulting clang binary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199025 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[Sparc] Add missing processor types: v7 and niagara
Venkatraman Govindaraju [Sat, 11 Jan 2014 23:56:13 +0000 (23:56 +0000)]
[Sparc] Add missing processor types: v7 and niagara

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199024 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM IAS: support emitting constant values in target expressions
Saleem Abdulrasool [Sat, 11 Jan 2014 23:03:48 +0000 (23:03 +0000)]
ARM IAS: support emitting constant values in target expressions

A 32-bit immediate value can be formed from a constant expression and loaded
into a register.  Add support to emit this into an object file.  Because this
value is a constant, a relocation must *not* be produced for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199023 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix broken CHECK lines.
Benjamin Kramer [Sat, 11 Jan 2014 21:06:00 +0000 (21:06 +0000)]
Fix broken CHECK lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199016 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLoopVectorizer: Enable strided memory accesses versioning per default
Arnold Schwaighofer [Sat, 11 Jan 2014 20:40:34 +0000 (20:40 +0000)]
LoopVectorizer: Enable strided memory accesses versioning per default

I saw no compile or execution time regressions on x86_64 -mavx -O3.

radar://13075509

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199015 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify...
Venkatraman Govindaraju [Sat, 11 Jan 2014 19:38:03 +0000 (19:38 +0000)]
[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199014 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agolit: Provide source locations in cfg files with older Python versions
Alp Toker [Sat, 11 Jan 2014 14:34:18 +0000 (14:34 +0000)]
lit: Provide source locations in cfg files with older Python versions

This commit prospectively brings the benefits of r198766 to older supported
Python versions (2.5+).

Tested with Python 2.6, 2.7, 3.1 and 3.3 (!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199009 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix 'ned' typo in doc comment
Alp Toker [Sat, 11 Jan 2014 14:01:43 +0000 (14:01 +0000)]
Fix 'ned' typo in doc comment

Patch by Jasper Neumann!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199007 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agolit: execfile() isn't present in Python 3.3
Alp Toker [Sat, 11 Jan 2014 13:27:28 +0000 (13:27 +0000)]
lit: execfile() isn't present in Python 3.3

On the other hand, exec(compile()) doesn't work in older Python versions in the
2.x series.

This commit introduces exec(compile()) with a fallback to plain exec(). That'll
hopefully hit the sweet spot in terms of version support.

Followup to r198766 which added enhanced source locations for lit cfg parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199006 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Actually nest pass managers correctly when parsing the pass
Chandler Carruth [Sat, 11 Jan 2014 12:06:47 +0000 (12:06 +0000)]
[PM] Actually nest pass managers correctly when parsing the pass
pipeline string. Add tests that cover this now that we have execution
dumping in the pass managers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199005 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Add names to passes under the new pass manager, and a debug output
Chandler Carruth [Sat, 11 Jan 2014 11:52:05 +0000 (11:52 +0000)]
[PM] Add names to passes under the new pass manager, and a debug output
mode that can be used to debug the execution of everything.

No support for analyses here, that will come later. This already helps
show parts of the opt commandline integration that isn't working. Tests
of that will start using it as the bugs are fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199004 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Somehow I missed the header guards on this file. Yikes!
Chandler Carruth [Sat, 11 Jan 2014 10:59:00 +0000 (10:59 +0000)]
[PM] Somehow I missed the header guards on this file. Yikes!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199003 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLoopVectorize.cpp: Appease MSC16.
NAKAMURA Takumi [Sat, 11 Jan 2014 09:59:27 +0000 (09:59 +0000)]
LoopVectorize.cpp: Appease MSC16.

Excuse me, I hope msc16 builders would be fine till its end day.
Introduce nullptr then. ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199001 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/Transforms/SampleProfile/syntax.ll: Eliminate locale-sensitive message...
NAKAMURA Takumi [Sat, 11 Jan 2014 09:23:52 +0000 (09:23 +0000)]
llvm/test/Transforms/SampleProfile/syntax.ll: Eliminate locale-sensitive message check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199000 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/CodeGen/X86/anyregcc.ll: Add explicit -mtriple=x86_64-unknown-unknown.
NAKAMURA Takumi [Sat, 11 Jan 2014 09:23:44 +0000 (09:23 +0000)]
llvm/test/CodeGen/X86/anyregcc.ll: Add explicit -mtriple=x86_64-unknown-unknown.

XMM(s) are really spilling for targeting Win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198999 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PM] Add (very skeletal) support to opt for running the new pass
Chandler Carruth [Sat, 11 Jan 2014 08:16:35 +0000 (08:16 +0000)]
[PM] Add (very skeletal) support to opt for running the new pass
manager. I cannot emphasize enough that this is a WIP. =] I expect it
to change a great deal as things stabilize, but I think its really
important to get *some* functionality here so that the infrastructure
can be tested more traditionally from the commandline.

The current design is looking something like this:

  ./bin/opt -passes='module(pass_a,pass_b,function(pass_c,pass_d))'

So rather than custom-parsed flags, there is a single flag with a string
argument that is parsed into the pass pipeline structure. This makes it
really easy to have nice structural properties that are very explicit.
There is one obvious and important shortcut. You can start off the
pipeline with a pass, and the minimal context of pass managers will be
built around the entire specified pipeline. This makes the common case
for tests super easy:

  ./bin/opt -passes=instcombine,sroa,gvn

But this won't introduce any of the complexity of the fully inferred old
system -- we only ever do this for the *entire* argument, and we only
look at the first pass. If the other passes don't fit in the pass
manager selected it is a hard error.

The other interesting aspect here is that I'm not relying on any
registration facilities. Such facilities may be unavoidable for
supporting plugins, but I have alternative ideas for plugins that I'd
like to try first. My plan is essentially to build everything without
registration until we hit an absolute requirement.

Instead of registration of pass names, there will be a library dedicated
to parsing pass names and the pass pipeline strings described above.
Currently, this is directly embedded into opt for simplicity as it is
very early, but I plan to eventually pull this into a library that opt,
bugpoint, and even Clang can depend on. It should end up as a good home
for things like the existing PassManagerBuilder as well.

There are a bunch of FIXMEs in the code for the parts of this that are
just stubbed out to make the patch more incremental. A quick list of
what's coming up directly after this:
- Support for function passes and building the structured nesting.
- Support for printing the pass structure, and FileCheck tests of all of
  this code.
- The .def-file based pass name parsing.
- IR priting passes and the corresponding tests.

Some obvious things that I'm not going to do right now, but am
definitely planning on as the pass manager work gets a bit further:
- Pull the parsing into library, including the builders.
- Thread the rest of the target stuff into the new pass manager.
- Wire support for the new pass manager up to llc.
- Plugin support.

Some things that I'd like to have, but are significantly lower on my
priority list. I'll get to these eventually, but they may also be places
where others want to contribute:
- Adding nice error reporting for broken pass pipeline descriptions.
- Typo-correction for pass names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198998 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[anyregcc] Fix callee-save mask for anyregcc
Juergen Ributzka [Sat, 11 Jan 2014 01:00:27 +0000 (01:00 +0000)]
[anyregcc] Fix callee-save mask for anyregcc

Use separate callee-save masks for XMM and YMM registers for anyregcc on X86 and
select the proper mask depending on the target cpu we compile for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198985 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert r198979 - accidental commit.
Eric Christopher [Sat, 11 Jan 2014 00:28:12 +0000 (00:28 +0000)]
Revert r198979 - accidental commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198981 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReformat.
Eric Christopher [Sat, 11 Jan 2014 00:23:18 +0000 (00:23 +0000)]
Reformat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198980 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdate function name and add some helpful comments.
Eric Christopher [Sat, 11 Jan 2014 00:23:16 +0000 (00:23 +0000)]
Update function name and add some helpful comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198979 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix odd whitespace.
Eric Christopher [Sat, 11 Jan 2014 00:23:11 +0000 (00:23 +0000)]
Fix odd whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198978 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoExtend and simplify the sample profile input file.
Diego Novillo [Fri, 10 Jan 2014 23:23:51 +0000 (23:23 +0000)]
Extend and simplify the sample profile input file.

1- Use the line_iterator class to read profile files.

2- Allow comments in profile file. Lines starting with '#'
   are completely ignored while reading the profile.

3- Add parsing support for discriminators and indirect call samples.

   Our external profiler can emit more profile information that we are
   currently not handling. This patch does not add new functionality to
   support this information, but it allows profile files to provide it.

   I will add actual support later on (for at least one of these
   features, I need support for DWARF discriminators in Clang).

   A sample line may contain the following additional information:

   Discriminator. This is used if the sampled program was compiled with
   DWARF discriminator support
   (http://wiki.dwarfstd.org/index.php?title=Path_Discriminators). This
   is currently only emitted by GCC and we just ignore it.

   Potential call targets and samples. If present, this line contains a
   call instruction. This models both direct and indirect calls. Each
   called target is listed together with the number of samples. For
   example,

                    130: 7  foo:3  bar:2  baz:7

   The above means that at relative line offset 130 there is a call
   instruction that calls one of foo(), bar() and baz(). With baz()
   being the relatively more frequent call target.

   Differential Revision: http://llvm-reviews.chandlerc.com/D2355

4- Simplify format of profile input file.

   This implements earlier suggestions to simplify the format of the
   sample profile file. The symbol table is not necessary and function
   profiles do not need to know the number of samples in advance.

   Differential Revision: http://llvm-reviews.chandlerc.com/D2419

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198973 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoPropagation of profile samples through the CFG.
Diego Novillo [Fri, 10 Jan 2014 23:23:46 +0000 (23:23 +0000)]
Propagation of profile samples through the CFG.

This adds a propagation heuristic to convert instruction samples
into branch weights. It implements a similar heuristic to the one
implemented by Dehao Chen on GCC.

The propagation proceeds in 3 phases:

1- Assignment of block weights. All the basic blocks in the function
   are initial assigned the same weight as their most frequently
   executed instruction.

2- Creation of equivalence classes. Since samples may be missing from
   blocks, we can fill in the gaps by setting the weights of all the
   blocks in the same equivalence class to the same weight. To compute
   the concept of equivalence, we use dominance and loop information.
   Two blocks B1 and B2 are in the same equivalence class if B1
   dominates B2, B2 post-dominates B1 and both are in the same loop.

3- Propagation of block weights into edges. This uses a simple
   propagation heuristic. The following rules are applied to every
   block B in the CFG:

   - If B has a single predecessor/successor, then the weight
     of that edge is the weight of the block.

   - If all the edges are known except one, and the weight of the
     block is already known, the weight of the unknown edge will
     be the weight of the block minus the sum of all the known
     edges. If the sum of all the known edges is larger than B's weight,
     we set the unknown edge weight to zero.

   - If there is a self-referential edge, and the weight of the block is
     known, the weight for that edge is set to the weight of the block
     minus the weight of the other incoming edges to that block (if
     known).

Since this propagation is not guaranteed to finalize for every CFG, we
only allow it to proceed for a limited number of iterations (controlled
by -sample-profile-max-propagate-iterations). It currently uses the same
GCC default of 100.

Before propagation starts, the pass builds (for each block) a list of
unique predecessors and successors. This is necessary to handle
identical edges in multiway branches. Since we visit all blocks and all
edges of the CFG, it is cleaner to build these lists once at the start
of the pass.

Finally, the patch fixes the computation of relative line locations.
The profiler emits lines relative to the function header. To discover
it, we traverse the compilation unit looking for the subprogram
corresponding to the function. The line number of that subprogram is the
line where the function begins. That becomes line zero for all the
relative locations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198972 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSpace formatting fix for r198966.
Tom Roeder [Fri, 10 Jan 2014 23:17:39 +0000 (23:17 +0000)]
Space formatting fix for r198966.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198971 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoConstant propagate MachineInstrClassName.
Roman Divacky [Fri, 10 Jan 2014 22:59:49 +0000 (22:59 +0000)]
Constant propagate MachineInstrClassName.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198969 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFixing build break: should be in the if statement, not outside.
Tom Roeder [Fri, 10 Jan 2014 22:55:25 +0000 (22:55 +0000)]
Fixing build break: should be in the if statement, not outside.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198966 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRestore the library dependency of LLVMgold on LTO; this was removed recently but
Tom Roeder [Fri, 10 Jan 2014 22:48:35 +0000 (22:48 +0000)]
Restore the library dependency of LLVMgold on LTO; this was removed recently but
is needed for LLVMgold to load in ld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198965 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a note about the old asm printer being removed.
Rafael Espindola [Fri, 10 Jan 2014 22:06:26 +0000 (22:06 +0000)]
Add a note about the old asm printer being removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198960 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAll backends use MC now.
Rafael Espindola [Fri, 10 Jan 2014 21:49:27 +0000 (21:49 +0000)]
All backends use MC now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198959 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUse the simpler version of sys::fs::remove when possible.
Rafael Espindola [Fri, 10 Jan 2014 21:40:29 +0000 (21:40 +0000)]
Use the simpler version of sys::fs::remove when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198958 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove remove_all. A compiler has no need for recursively deleting a directory.
Rafael Espindola [Fri, 10 Jan 2014 20:36:42 +0000 (20:36 +0000)]
Remove remove_all. A compiler has no need for recursively deleting a directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198955 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLTO: whitespace changes
Duncan P. N. Exon Smith [Fri, 10 Jan 2014 20:24:35 +0000 (20:24 +0000)]
LTO: whitespace changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198954 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLoopVectorizer: Handle strided memory accesses by versioning
Arnold Schwaighofer [Fri, 10 Jan 2014 18:20:32 +0000 (18:20 +0000)]
LoopVectorizer: Handle strided memory accesses by versioning

 for (i = 0; i < N; ++i)
   A[i * Stride1] += B[i * Stride2];

We take loops like this and check that the symbolic strides 'Strided1/2' are one
and drop to the scalar loop if they are not.

This is currently disabled by default and hidden behind the flag
'enable-mem-access-versioning'.

radar://13075509

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198950 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSCEVRewriter: Optionally interpret constants in value map as SCEVConstant
Arnold Schwaighofer [Fri, 10 Jan 2014 18:20:29 +0000 (18:20 +0000)]
SCEVRewriter: Optionally interpret constants in value map as SCEVConstant

An upcoming loop vectorizer commit will want to replace a SCEVUnknown(Value*)
by a SCEVConstant. This commit modifies the SCEVParameterRewriter to support
this. The SCEVParameterRewriter constructor can optionally specify to follow
this behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198949 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAmending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test...
Artyom Skrobov [Fri, 10 Jan 2014 16:49:49 +0000 (16:49 +0000)]
Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMust not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
Artyom Skrobov [Fri, 10 Jan 2014 16:42:55 +0000 (16:42 +0000)]
Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: fix regression caused by r198914
Saleem Abdulrasool [Fri, 10 Jan 2014 16:22:47 +0000 (16:22 +0000)]
ARM: fix regression caused by r198914

The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8