oota-llvm.git
9 years ago[x86] Reduce text duplication for similar operand class declarations in tablegen...
Craig Topper [Mon, 5 Jan 2015 08:19:03 +0000 (08:19 +0000)]
[x86] Reduce text duplication for similar operand class declarations in tablegen instruction info. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225153 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Fix the immediate size to match the address size in the operand types for the...
Craig Topper [Mon, 5 Jan 2015 08:18:59 +0000 (08:18 +0000)]
[X86] Fix the immediate size to match the address size in the operand types for the move to/from absolute memory instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225152 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Remove unused operand type from disassembler handling. NFC
Craig Topper [Mon, 5 Jan 2015 08:18:52 +0000 (08:18 +0000)]
[X86] Remove unused operand type from disassembler handling. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225151 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Enable speculation of cttz/ctlz
Hal Finkel [Mon, 5 Jan 2015 05:24:42 +0000 (05:24 +0000)]
[PowerPC] Enable speculation of cttz/ctlz

PPC has an instruction for ctlz with defined zero behavior, and our lowering of
cttz (provided by DAGCombine) is also efficient and branchless, so speculating
these makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225150 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Apply a somewhat heavy and unpleasant hammer to fix PR22093, an
Chandler Carruth [Mon, 5 Jan 2015 04:17:53 +0000 (04:17 +0000)]
[SROA] Apply a somewhat heavy and unpleasant hammer to fix PR22093, an
assert out of the new pre-splitting in SROA.

This fix makes the code do what was originally intended -- when we have
a store of a load both dealing in the same alloca, we force them to both
be pre-split with identical offsets. This is really quite hard to do
because we can keep discovering problems as we go along. We have to
track every load over the current alloca which for any resaon becomes
invalid for pre-splitting, and go back to remove all stores of those
loads. I've included a couple of test cases derived from PR22093 that
cover the different ways this can happen. While that PR only really
triggered the first of these two, its the same fundamental issue.

The other challenge here is documented in a FIXME now. We end up being
quite a bit more aggressive for pre-splitting when loads and stores
don't refer to the same alloca. This aggressiveness comes at the cost of
introducing potentially redundant loads. It isn't clear that this is the
right balance. It might be considerably better to require that we only
do pre-splitting when we can presplit every load and store involved in
the entire operation. That would give more consistent if conservative
results. Unfortunately, it requires a non-trivial change to the actual
pre-splitting operation in order to correctly handle cases where we end
up pre-splitting stores out-of-order. And it isn't 100% clear that this
is the right direction, although I'm starting to suspect that it is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225149 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LangRef] Correct a typo
Hal Finkel [Mon, 5 Jan 2015 04:05:21 +0000 (04:05 +0000)]
[LangRef] Correct a typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225148 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Materialize i64 constants using rotation with masking
Hal Finkel [Mon, 5 Jan 2015 03:41:38 +0000 (03:41 +0000)]
[PowerPC] Materialize i64 constants using rotation with masking

r225135 added the ability to materialize i64 constants using rotations in order
to reduce the instruction count. Sometimes we can use a rotation only with some
extra masking, so that we take advantage of the fact that generating a bunch of
extra higher-order 1 bits is easy using li/lis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225147 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Cleanup a place where I forgot to update the header guards when
Chandler Carruth [Mon, 5 Jan 2015 03:03:31 +0000 (03:03 +0000)]
[PM] Cleanup a place where I forgot to update the header guards when
renaming a file from AssumptionTracker.h to AssumptionCache.h.

Thanks to Philip Reames for noticing and pointing it out in code review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225146 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Switch the new pass manager to use a reference-based API for IR
Chandler Carruth [Mon, 5 Jan 2015 02:47:05 +0000 (02:47 +0000)]
[PM] Switch the new pass manager to use a reference-based API for IR
units.

This was debated back and forth a bunch, but using references is now
clearly cleaner. Of all the code written using pointers thus far, in
only one place did it really make more sense to have a pointer. In most
cases, this just removes immediate dereferencing from the code. I think
it is much better to get errors on null IR units earlier, potentially
at compile time, than to delay it.

Most notably, the legacy pass manager uses references for its routines
and so as more and more code works with both, the use of pointers was
likely to become really annoying. I noticed this when I ported the
domtree analysis over and wrote the entire thing with references only to
have it fail to compile. =/ It seemed better to switch now than to
delay. We can, of course, revisit this is we learn that references are
really problematic in the API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225145 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Wire up support for explicitly running the verifier pass.
Chandler Carruth [Mon, 5 Jan 2015 00:08:53 +0000 (00:08 +0000)]
[PM] Wire up support for explicitly running the verifier pass.

The required functionality has been there for some time, but I never
managed to actually wire it into the command line registry of passes.
Let's do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225144 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Cleanup a const_cast and other machinery left over in this code
Chandler Carruth [Sun, 4 Jan 2015 23:13:57 +0000 (23:13 +0000)]
[PM] Cleanup a const_cast and other machinery left over in this code
from before I removed thet non-const use of the function.

The unused variable that held the const_cast was already kindly removed
by Michael.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225143 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][SSE] Added vector packing test for pr12412
Simon Pilgrim [Sun, 4 Jan 2015 19:08:03 +0000 (19:08 +0000)]
[X86][SSE] Added vector packing test for pr12412

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225138 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][SSE] Added vector integer truncation tests - based off pr15524
Simon Pilgrim [Sun, 4 Jan 2015 17:52:00 +0000 (17:52 +0000)]
[X86][SSE] Added vector integer truncation tests - based off pr15524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225137 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Materialize i64 constants using rotation
Hal Finkel [Sun, 4 Jan 2015 15:43:55 +0000 (15:43 +0000)]
[PowerPC] Materialize i64 constants using rotation

Materializing full 64-bit constants on PPC64 can be expensive, requiring up to
5 instructions depending on the locations of the non-zero bits. Sometimes
materializing a rotated constant, and then applying the inverse rotation, requires
fewer instructions than the direct method. If so, do that instead.

In r225132, I added support for forming constants using bit inversion. In
effect, this reverts that commit and replaces it with rotation support. The bit
inversion is useful for turning constants that are mostly ones into ones that
are mostly zeros (thus enabling a more-efficient shift-based materialization),
but the same effect can be obtained by using negative constants and a rotate,
and that is at least as efficient, if not more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225135 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix unused variable warning for non-asserts builds. NFC.
Michael Kuperstein [Sun, 4 Jan 2015 13:35:44 +0000 (13:35 +0000)]
Fix unused variable warning for non-asserts builds. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225133 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Materialize i64 constants using bit inversion
Hal Finkel [Sun, 4 Jan 2015 12:35:03 +0000 (12:35 +0000)]
[PowerPC] Materialize i64 constants using bit inversion

Materializing full 64-bit constants on PPC64 can be expensive, requiring up to
5 instructions depending on the locations of the non-zero bits. Sometimes
materializing the bit-reversed constant, and then flipping the bits, requires
fewer instructions than the direct method. If so, do that instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225132 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Split the AssumptionTracker immutable pass into two separate APIs:
Chandler Carruth [Sun, 4 Jan 2015 12:03:27 +0000 (12:03 +0000)]
[PM] Split the AssumptionTracker immutable pass into two separate APIs:
a cache of assumptions for a single function, and an immutable pass that
manages those caches.

The motivation for this change is two fold. Immutable analyses are
really hacks around the current pass manager design and don't exist in
the new design. This is usually OK, but it requires that the core logic
of an immutable pass be reasonably partitioned off from the pass logic.
This change does precisely that. As a consequence it also paves the way
for the *many* utility functions that deal in the assumptions to live in
both pass manager worlds by creating an separate non-pass object with
its own independent API that they all rely on. Now, the only bits of the
system that deal with the actual pass mechanics are those that actually
need to deal with the pass mechanics.

Once this separation is made, several simplifications become pretty
obvious in the assumption cache itself. Rather than using a set and
callback value handles, it can just be a vector of weak value handles.
The callers can easily skip the handles that are null, and eventually we
can wrap all of this up behind a filter iterator.

For now, this adds boiler plate to the various passes, but this kind of
boiler plate will end up making it possible to port these passes to the
new pass manager, and so it will end up factored away pretty reasonably.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225131 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombine: match can find ConstantExprs, don't assume we have a Value
David Majnemer [Sun, 4 Jan 2015 07:36:02 +0000 (07:36 +0000)]
InstCombine: match can find ConstantExprs, don't assume we have a Value

We assumed the output of a match was a Value, this would cause us to
assert because we would fail a cast<>.  Instead, use a helper in the
Operator family to hide the distinction between Value and Constant.

This fixes PR22087.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225127 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoValueTracking: ComputeNumSignBits should tolerate misshapen phi nodes
David Majnemer [Sun, 4 Jan 2015 07:06:53 +0000 (07:06 +0000)]
ValueTracking: ComputeNumSignBits should tolerate misshapen phi nodes

PHI nodes can have zero operands in the middle of a transform.  It is
expected that utilities in Analysis don't freak out when this happens.

Note that it is considered invalid to allow these misshapen phi nodes to
make it to another pass.

This fixes PR22086.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225126 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[APFloat][ADT] Fix sign handling logic for FMA results that truncate to zero.
Lang Hames [Sun, 4 Jan 2015 01:20:55 +0000 (01:20 +0000)]
[APFloat][ADT] Fix sign handling logic for FMA results that truncate to zero.

This patch adds a check for underflow when truncating results back to lower
precision at the end of an FMA. The additional sign handling logic in
APFloat::fusedMultiplyAdd should only be performed when the result of the
addition step of the FMA (in full precision) is exactly zero, not when the
result underflows to zero.

Unit tests for this case and related signed zero FMA results are included.

Fixes <rdar://problem/18925551>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225123 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agollvm-readobj: add support to dump COFF export tables
Saleem Abdulrasool [Sat, 3 Jan 2015 21:35:09 +0000 (21:35 +0000)]
llvm-readobj: add support to dump COFF export tables

This enhances llvm-readobj to print out the COFF export table, similar to the
-coff-import option.  This is useful for testing in lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225120 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: permit tail calls to weak externals on COFF
Saleem Abdulrasool [Sat, 3 Jan 2015 21:35:00 +0000 (21:35 +0000)]
ARM: permit tail calls to weak externals on COFF

Weak externals are resolved statically, so we can actually generate the tail
call on PE/COFF targets without breaking the requirements.  It is questionable
whether we want to propagate the current behaviour for MachO as the requirements
are part of the ARM ELF specifications, and it seems that prior to the SVN
r215890, we would have tail'ed the call.  For now, be conservative and only
permit it on PE/COFF where the call will always be fully resolved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225119 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC/BlockPlacement] Allow target to provide a per-loop alignment preference
Hal Finkel [Sat, 3 Jan 2015 17:58:24 +0000 (17:58 +0000)]
[PowerPC/BlockPlacement] Allow target to provide a per-loop alignment preference

The existing code provided for specifying a global loop alignment preference.
However, the preferred loop alignment might depend on the loop itself. For
recent POWER cores, loops between 5 and 8 instructions should have 32-byte
alignment (while the others are better with 16-byte alignment) so that the
entire loop will fit in one i-cache line.

To support this, getPrefLoopAlignment has been made virtual, and can be
provided with an optional MachineLoop* so the target can inspect the loop
before answering the query. The default behavior, as before, is to return the
value set with setPrefLoopAlignment. MachineBlockPlacement now queries the
target for each loop instead of only once per function. There should be no
functional change for other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225117 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Use 16-byte alignment for modern cores for functions/loops
Hal Finkel [Sat, 3 Jan 2015 14:58:25 +0000 (14:58 +0000)]
[PowerPC] Use 16-byte alignment for modern cores for functions/loops

Most modern PowerPC cores prefer that functions and loops start on
16-byte-aligned boundaries (*), so instruct block placement, etc. to make this
happen. The branch selector has also been adjusted so account for the extra
nops that might now be inserted before loop headers.

(*) Some cores actually prefer other alignments for small loops, but that will
    be addressed in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225115 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMinor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers.
Craig Topper [Sat, 3 Jan 2015 08:16:34 +0000 (08:16 +0000)]
Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers.

Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225114 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix some formatting in tablegen output.
Craig Topper [Sat, 3 Jan 2015 08:16:29 +0000 (08:16 +0000)]
Fix some formatting in tablegen output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225113 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReplace some 'unreachable' comments with llvm_unreachable.
Craig Topper [Sat, 3 Jan 2015 08:16:14 +0000 (08:16 +0000)]
Replace some 'unreachable' comments with llvm_unreachable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225112 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoValueTracking: Make computeKnownBits for Arguments a little more clear
David Majnemer [Sat, 3 Jan 2015 02:33:25 +0000 (02:33 +0000)]
ValueTracking: Make computeKnownBits for Arguments a little more clear

We would sometimes leave the out-param APInts untouched while going
through computeKnownBits.  While I don't know of a way to trigger a bug
involving this in practice, it goes against the overall design of
computeKnownBits.

Found via code inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225109 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Add support for the CMPB instruction
Hal Finkel [Sat, 3 Jan 2015 01:16:37 +0000 (01:16 +0000)]
[PowerPC] Add support for the CMPB instruction

Newer POWER cores, and the A2, support the cmpb instruction. This instruction
compares its operands, treating each of the 8 bytes in the GPRs separately,
returning a 'mask' result of 0 (for false) or -1 (for true) in each byte.

Code generation support is added, in the form of a PPCISelDAGToDAG
DAG-preprocessing routine, that recognizes patterns close to what the
instruction computes (either exactly, or related by a constant masking
operation), and generates the cmpb instruction (along with any necessary
constant masking operation). This can be expanded if use cases arise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225106 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] simplify the tracing code, make it use the same guard variables as coverage
Kostya Serebryany [Sat, 3 Jan 2015 00:54:43 +0000 (00:54 +0000)]
[asan] simplify the tracing code, make it use the same guard variables as coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225103 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX...
Craig Topper [Sat, 3 Jan 2015 00:00:20 +0000 (00:00 +0000)]
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Use 32-bit sign extended immediate for 64-bit LOCK_ArithBinOp with sign extende...
Craig Topper [Sat, 3 Jan 2015 00:00:14 +0000 (00:00 +0000)]
[X86] Use 32-bit sign extended immediate for 64-bit LOCK_ArithBinOp with sign extended immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225098 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Add proper documentation for the ModulePassManager and
Chandler Carruth [Fri, 2 Jan 2015 23:34:39 +0000 (23:34 +0000)]
[PM] Add proper documentation for the ModulePassManager and
FunctionPassManager. These never got documented, likely due to the
clutter of this header file. This fixes another problem people noticed
when they started trying to use the new pass manager.

I've also used this to document the aspirational constraints I would
like to hold passes to. I don't really have a better place to document
such things at this point, but eventually will probably create a proper
.rst file and page for the LLVM pass infrastructure that carries such
high-level concerns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225097 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Actually include the correct file name. Sorry for the breakage.
Chandler Carruth [Fri, 2 Jan 2015 23:25:16 +0000 (23:25 +0000)]
[PM] Actually include the correct file name. Sorry for the breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225096 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Lift the majority of the template boilerplate used to implement the
Chandler Carruth [Fri, 2 Jan 2015 23:16:59 +0000 (23:16 +0000)]
[PM] Lift the majority of the template boilerplate used to implement the
concept-based polymorphism in the pass manager to a separate header.

I got feedback from someone reading the code and trying to use it that
this was really making it hard to dive in and start using these APIs and
that makes a lot of sense.

This only requires a moderate amount of gymnastics to separate in this
way, namely rinsing the PreservedAnalysis object through a template
argument in a few places so that it is dependent and we only examine it
on instantiation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225094 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PM] Fix some formatting where clang-format has improved recently.
Chandler Carruth [Fri, 2 Jan 2015 22:51:44 +0000 (22:51 +0000)]
[PM] Fix some formatting where clang-format has improved recently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225092 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReformat statepoint documentation and fix a couple of typos
Philip Reames [Fri, 2 Jan 2015 19:46:49 +0000 (19:46 +0000)]
Reformat statepoint documentation and fix a couple of typos

Patch by Ramkumar Ramachandra <artagnon@gmail.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225084 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImproved comments. No functional change intended.
Andrea Di Biagio [Fri, 2 Jan 2015 10:47:46 +0000 (10:47 +0000)]
Improved comments. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225080 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Bring some better consistency to the naming of the move to/from %al/ax/eax...
Craig Topper [Fri, 2 Jan 2015 07:36:23 +0000 (07:36 +0000)]
[X86] Bring some better consistency to the naming of the move to/from %al/ax/eax/rax with memory offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225078 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombine: Detect when llvm.umul.with.overflow always overflows
David Majnemer [Fri, 2 Jan 2015 07:29:47 +0000 (07:29 +0000)]
InstCombine: Detect when llvm.umul.with.overflow always overflows

We know overflow always occurs if both ~LHSKnownZero * ~RHSKnownZero
and LHSKnownOne * RHSKnownOne overflow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225077 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAnalysis: Reformulate WillNotOverflowUnsignedMul for reusability
David Majnemer [Fri, 2 Jan 2015 07:29:43 +0000 (07:29 +0000)]
Analysis: Reformulate WillNotOverflowUnsignedMul for reusability

WillNotOverflowUnsignedMul's smarts will live in ValueTracking as
computeOverflowForUnsignedMul.  It now returns a tri-state result:
never overflows, always overflows and sometimes overflows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225076 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Make the instructions that use AdSize16/32/64 co-exist together without using...
Craig Topper [Fri, 2 Jan 2015 07:02:25 +0000 (07:02 +0000)]
[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.

This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225075 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Teach SROA to be more aggressive in splitting now that we have
Chandler Carruth [Fri, 2 Jan 2015 03:55:54 +0000 (03:55 +0000)]
[SROA] Teach SROA to be more aggressive in splitting now that we have
a pre-splitting pass over loads and stores.

Historically, splitting could cause enough problems that I hamstrung the
entire process with a requirement that splittable integer loads and
stores must cover the entire alloca. All smaller loads and stores were
unsplittable to prevent chaos from ensuing. With the new pre-splitting
logic that does load/store pair splitting I introduced in r225061, we
can now very nicely handle arbitrarily splittable loads and stores. In
order to fully benefit from these smarts, we need to mark all of the
integer loads and stores as splittable.

However, we don't actually want to rewrite partitions with all integer
loads and stores marked as splittable. This will fail to extract scalar
integers from aggregates, which is kind of the point of SROA. =] In
order to resolve this, what we really want to do is only do
pre-splitting on the alloca slices with integer loads and stores fully
splittable. This allows us to uncover all non-integer uses of the alloca
that would benefit from a split in an integer load or store (and where
introducing the split is safe because it is just memory transfer from
a load to a store). Once done, we make all the non-whole-alloca integer
loads and stores unsplittable just as they have historically been,
repartition and rewrite.

The result is that when there are integer loads and stores anywhere
within an alloca (such as from a memcpy of a sub-object of a larger
object), we can split them up if there are non-integer components to the
aggregate hiding beneath. I've added the challenging test cases to
demonstrate how this is able to promote to scalars even a case where we
have even *partially* overlapping loads and stores.

This restores the single-store behavior for small arrays of i8s which is
really nice. I've restored both the little endian testing and big endian
testing for these exactly as they were prior to r225061. It also forced
me to be more aggressive in an alignment test to actually defeat SROA.
=] Without the added volatiles there, we actually split up the weird i16
loads and produce nice double allocas with better alignment.

This also uncovered a number of bugs where we failed to handle
splittable load and store slices which didn't have a begininng offset of
zero. Those fixes are included, and without them the existing test cases
explode in glorious fireworks. =]

I've kept support for leaving whole-alloca integer loads and stores as
splittable even for the purpose of rewriting, but I think that's likely
no longer needed. With the new pre-splitting, we might be able to remove
all the splitting support for loads and stores from the rewriter. Not
doing that in this patch to try to isolate any performance regressions
that causes in an easy to find and revert chunk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225074 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Make the computation of adjusted pointers not leak GEP
Chandler Carruth [Fri, 2 Jan 2015 02:47:38 +0000 (02:47 +0000)]
[SROA] Make the computation of adjusted pointers not leak GEP
instructions.

I noticed this when working on dialing up how aggressively we can
pre-split loads and stores. My test case wasn't passing because dead
GEPs into the allocas persisted when they were built by this routine.
This isn't terribly harmful, we still rewrote and promoted the alloca
and I can't conceive of how to cause this to happen in a case where we
will keep the exact same alloca but rewrite and promote the uses of it.
If that ever happened, we'd get an assert out of mem2reg.

So I don't have a direct test case yet, but the subsequent commit's test
case wouldn't pass without this. There are other problems fixed by this
patch that I spotted purely by inspection such as the fact that
getAdjustedPtr could have actually deleted dead base pointers. I don't
know how to get a base pointer to go into getAdjustedPtr today, so
I think this bug could never have manifested (and I certainly can't
write a test case for it) but, it wasn't the intent of the code. The
code really just wanted to GC the new instructions built. That can be
done more directly by comparing with the base pointer which is the only
non-new instruction that this code can return.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225073 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Add a test case for r225068 / PR22080.
Chandler Carruth [Fri, 2 Jan 2015 00:34:29 +0000 (00:34 +0000)]
[SROA] Add a test case for r225068 / PR22080.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225070 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Fix the loop exit placement to be prior to indexing the splits
Chandler Carruth [Fri, 2 Jan 2015 00:10:22 +0000 (00:10 +0000)]
[SROA] Fix the loop exit placement to be prior to indexing the splits
array. This prevents it from walking out of bounds on the splits array.

Bug found with the existing tests by ASan and by the MSVC debug build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225069 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Fix two total think-os in r225061 that should have been caught on
Chandler Carruth [Thu, 1 Jan 2015 23:26:16 +0000 (23:26 +0000)]
[SROA] Fix two total think-os in r225061 that should have been caught on
a +asserts bootstrap, but my bootstrap had asserts off. Oops.

Anyways, in some places it is reasonable to cast (as a sanity check) the
pointer operand to a load or store to an instruction within SROA --
namely when the pointer operand is expected to be derived from an
alloca, and thus always an instruction. However, the pre-splitting code
also deals with loads and stores to non-alloca pointers and there we
need to just use the Value*. Nothing about the code relied on the
instruction cast, it was only there essentially as an invariant
assertion. Remove the two that don't actually hold.

This should fix the proximate issue in PR22080, but I'm also doing an
asserts bootstrap myself to see if there are other issues lurking.

I'll craft a reduced test case in a moment, but I wanted to get the tree
healthy as quickly as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225068 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] use UINT64_C instead of ul
Hal Finkel [Thu, 1 Jan 2015 19:33:59 +0000 (19:33 +0000)]
[PowerPC] use UINT64_C instead of ul

Attempting to fix PR22078 (building on 32-bit systems) by replacing my careless
use of 1ul to be a uint64_t constant with UINT64_C(1).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225066 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "Just use a using directive in SmallMapVector instead of inheriting from MapVe...
Michael Gottesman [Thu, 1 Jan 2015 13:54:05 +0000 (13:54 +0000)]
Revert "Just use a using directive in SmallMapVector instead of inheriting from MapVector itself."

This reverts commit r225059. I think MSVC 2012 has a problem with this. This is
an attempt to fix one of the MSVC 2012 bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225065 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r225053: Add an ArrayRef upcasting constructor from ArrayRef<U*> -> ArrayRef...
Chandler Carruth [Thu, 1 Jan 2015 13:01:25 +0000 (13:01 +0000)]
Revert r225053: Add an ArrayRef upcasting constructor from ArrayRef<U*> -> ArrayRef<T*> where T is a base of U.

This appears to have broken at least the windows build bots due to
compile errors in the predicate that didn't simply supress the overload.
I'm not sure what the fix is, and the bots have been broken for a long
time now so I'm just reverting until Michael can figure out a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225064 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Switch to using a more direct debug logging technique in one part
Chandler Carruth [Thu, 1 Jan 2015 12:56:47 +0000 (12:56 +0000)]
[SROA] Switch to using a more direct debug logging technique in one part
of my new load and store splitting, and fix a bug where it logged
a totally irrelevant slice rather than the actual slice in question.

The logging here previously worked because we used to place new slices
onto the back of the core sequence, but that caused other problems.
I updated the actual code to store new slices in their own vector but
didn't update the logging. There isn't a good way to reuse the logging
any more, and frankly it wasn't needed. We can directly log this bit
more easily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225063 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Fix formatting with clang-format which I managed to fail to do
Chandler Carruth [Thu, 1 Jan 2015 12:01:03 +0000 (12:01 +0000)]
[SROA] Fix formatting with clang-format which I managed to fail to do
prior to committing r225061. Sorry for that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225062 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Teach SROA how to much more intelligently handle split loads and
Chandler Carruth [Thu, 1 Jan 2015 11:54:38 +0000 (11:54 +0000)]
[SROA] Teach SROA how to much more intelligently handle split loads and
stores.

When there are accesses to an entire alloca with an integer
load or store as well as accesses to small pieces of the alloca, SROA
splits up the large integer accesses. In order to do that, it uses bit
math to merge the small accesses into large integers. While this is
effective, it produces insane IR that can cause significant problems in
the rest of the optimizer:

- It can cause load and store mismatches with GVN on the non-alloca side
  where we end up loading an i64 (or some such) rather than loading
  specific elements that are stored.
- We can't always get rid of the integer bit math, which is why we can't
  always fix the loads and stores to work well with GVN.
- This is especially bad when we have operations that mix poorly with
  integer bit math such as floating point operations.
- It will block things like the vectorizer which might be able to handle
  the scalar stores that underly the aggregate.

At the same time, we can't just directly split up these loads and stores
in all cases. If there is actual integer arithmetic involved on the
values, then using integer bit math is actually the perfect lowering
because we can often combine it heavily with the surrounding math.

The solution this patch provides is to find places where SROA is
partitioning aggregates into small elements, and look for splittable
loads and stores that it can split all the way to some other adjacent
load and store. These are uniformly the cases where failing to split the
loads and stores hurts the optimizer that I have seen, and I've looked
extensively at the code produced both from more and less aggressive
approaches to this problem.

However, it is quite tricky to actually do this in SROA. We may have
loads and stores to the same alloca, or other complex patterns that are
hard to handle. This complexity leads to the somewhat subtle algorithm
implemented here. We have to do this entire process as a separate pass
over the partitioning of the alloca, and split up all of the loads prior
to splitting the stores so that we can handle safely the cases of
overlapping, including partially overlapping, loads and stores to the
same alloca. We also have to reconstitute the post-split slice
configuration so we can avoid iterating again over all the alloca uses
(the slow part of SROA). But we also have to ensure that when we split
up loads and stores to *other* allocas, we *do* re-iterate over them in
SROA to adapt to the more refined partitioning now required.

With this, I actually think we can fix a long-standing TODO in SROA
where I avoided splitting as many loads and stores as probably should be
splittable. This limitation historically mitigated the fallout of all
the bad things mentioned above. Now that we have more intelligent
handling, I plan to remove the FIXME and more aggressively mark integer
loads and stores as splittable. I'll do that in a follow-up patch to
help with bisecting any fallout.

The net result of this change should be more fine-grained and accurate
scalars being formed out of aggregates. At the very least, Clang now
generates perfect code for this high-level test case using
std::complex<float>:

  #include <complex>

  void g1(std::complex<float> &x, float a, float b) {
    x += std::complex<float>(a, b);
  }
  void g2(std::complex<float> &x, float a, float b) {
    x -= std::complex<float>(a, b);
  }

  void foo(const std::complex<float> &x, float a, float b,
           std::complex<float> &x1, std::complex<float> &x2) {
    std::complex<float> l1 = x;
    g1(l1, a, b);
    std::complex<float> l2 = x;
    g2(l2, a, b);
    x1 = l1;
    x2 = l2;
  }

This code isn't just hypothetical either. It was reduced out of the hot
inner loops of essentially every part of the Eigen math library when
using std::complex<float>. Those loops would consistently and
pervasively hop between the floating point unit and the integer unit due
to bit math extraction and insertion of floating point values that were
"stored" in a 64-bit integer register around the loop backedge.

So far, this change has passed a bootstrap and I have done some other
testing and so far, no issues. That doesn't mean there won't be though,
so I'll be prepared to help with any fallout. If you performance swings
in particular, please let me know. I'm very curious what all the impact
of this change will be. Stay tuned for the follow-up to also split more
integer loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225061 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoJust use a using directive in SmallMapVector instead of inheriting from MapVector...
Michael Gottesman [Thu, 1 Jan 2015 08:05:41 +0000 (08:05 +0000)]
Just use a using directive in SmallMapVector instead of inheriting from MapVector itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225059 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Improve instruction selection bit-permuting operations (64-bit)
Hal Finkel [Thu, 1 Jan 2015 02:53:29 +0000 (02:53 +0000)]
[PowerPC] Improve instruction selection bit-permuting operations (64-bit)

This is the second installment of improvements to instruction selection for "bit
permutation" instruction sequences. r224318 added logic for instruction
selection for 32-bit bit permutation sequences, and this adds lowering for
64-bit sequences. The 64-bit sequences are more complicated than the 32-bit
ones because:
  a) the 64-bit versions of the 32-bit rotate-and-mask instructions
     work by replicating the lower 32-bits of the value-to-be-rotated into the
     upper 32 bits -- and integrating this into the cost modeling for the various
     bit group operations is non-trivial
  b) unlike the 32-bit instructions in 32-bit mode, the rotate-and-mask instructions
     cannot, in one instruction, specify the
     mask starting index, the mask ending index, and the rotation factor. Also,
     forming arbitrary 64-bit constants is more complicated than in 32-bit mode
     because the number of instructions necessary is value dependent.

Plus, support for 'late masking' was added: it is sometimes more efficient to
treat the overall value as if it had no mandatory zero bits when planning the
bit-group insertions, and then mask them in at the very end. Unfortunately, as
the structure of the bit groups is different in the two cases, the more
feasible implementation technique was to generate both instruction sequences,
and then pick the shorter one.

And finally, we now generate reasonable code for i64 bswap:

        rldicl 5, 3, 16, 0
        rldicl 4, 3, 8, 0
        rldicl 6, 3, 24, 0
        rldimi 4, 5, 8, 48
        rldicl 5, 3, 32, 0
        rldimi 4, 6, 16, 40
        rldicl 6, 3, 48, 0
        rldimi 4, 5, 24, 32
        rldicl 5, 3, 56, 0
        rldimi 4, 6, 40, 16
        rldimi 4, 5, 48, 8
        rldimi 4, 3, 56, 0

vs. what we used to produce:

        li 4, 255
        rldicl 5, 3, 24, 40
        rldicl 6, 3, 40, 24
        rldicl 7, 3, 56, 8
        sldi 8, 3, 8
        sldi 10, 3, 24
        sldi 12, 3, 40
        rldicl 0, 3, 8, 56
        sldi 9, 4, 32
        sldi 11, 4, 40
        sldi 4, 4, 48
        andi. 5, 5, 65280
        andis. 6, 6, 255
        andis. 7, 7, 65280
        sldi 3, 3, 56
        and 8, 8, 9
        and 4, 12, 4
        and 9, 10, 11
        or 6, 7, 6
        or 5, 5, 0
        or 3, 3, 4
        or 7, 9, 8
        or 4, 6, 5
        or 3, 3, 7
        or 3, 3, 4

which is 12 instructions, instead of 25, and seems optimal (at least in terms
of code size).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225056 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd 2x constructors for TinyPtrVector, one that takes in one elemenet and the other...
Michael Gottesman [Wed, 31 Dec 2014 23:33:24 +0000 (23:33 +0000)]
Add 2x constructors for TinyPtrVector, one that takes in one elemenet and the other that takes in an ArrayRef<EltTy>

Currently one can only construct an empty TinyPtrVector. These are just missing
elements of the API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225055 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a SmallMapVector class that is a MapVector with a Map of SmallDenseMap and a...
Michael Gottesman [Wed, 31 Dec 2014 23:33:21 +0000 (23:33 +0000)]
Add a SmallMapVector class that is a MapVector with a Map of SmallDenseMap and a Vector of SmallVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225054 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd an ArrayRef upcasting constructor from ArrayRef<U*> -> ArrayRef<T*> where T is...
Michael Gottesman [Wed, 31 Dec 2014 23:33:18 +0000 (23:33 +0000)]
Add an ArrayRef upcasting constructor from ArrayRef<U*> -> ArrayRef<T*> where T is a base of U.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225053 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombine: fsub nsz 0, X ==> fsub nsz -0.0, X
Sanjay Patel [Wed, 31 Dec 2014 22:14:05 +0000 (22:14 +0000)]
InstCombine: fsub nsz 0, X ==> fsub nsz -0.0, X

Some day the backend may handle instruction-level fast math flags and make
this transform unnecessary, but it's still better practice to use the canonical
representation of fneg when possible (use a -0.0).

This is a partial fix for PR20870 ( http://llvm.org/bugs/show_bug.cgi?id=20870 ).
See also http://reviews.llvm.org/D6723.

Differential Revision: http://reviews.llvm.org/D6731

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225050 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd r224985 back with a fix.
Rafael Espindola [Wed, 31 Dec 2014 17:19:34 +0000 (17:19 +0000)]
Add r224985 back with a fix.

The issues was that AArch64 has additional restrictions on when local
relocations can be used. We have to take those into consideration when
deciding to put a L symbol in the symbol table or not.

Original message:

Remove doesSectionRequireSymbols.

In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225048 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReverting 225045 and 225043 and XFAIL multiline.ll on hexagon
Colin LeMahieu [Wed, 31 Dec 2014 17:14:35 +0000 (17:14 +0000)]
Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225047 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a test for the recent compiler-rt build failure.
Rafael Espindola [Wed, 31 Dec 2014 16:58:05 +0000 (16:58 +0000)]
Add a test for the recent compiler-rt build failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225046 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Removing assertion to appease buildbot until I can reproduce the problem
Colin LeMahieu [Wed, 31 Dec 2014 16:20:00 +0000 (16:20 +0000)]
[Hexagon] Removing assertion to appease buildbot until I can reproduce the problem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225045 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "Remove doesSectionRequireSymbols."
Rafael Espindola [Wed, 31 Dec 2014 16:06:48 +0000 (16:06 +0000)]
Revert "Remove doesSectionRequireSymbols."

This reverts commit r224985.

I am investigating why it made an Apple bot unhappy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225044 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations...
Colin LeMahieu [Wed, 31 Dec 2014 15:57:38 +0000 (15:57 +0000)]
[Hexagon] Changing an llvm_unreachable to an assertion and returning 0.  Relocations aren't implemented yet but we don't need to abort for this in release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225043 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Update disassembler tests for absolute move instructions to check the encodings...
Craig Topper [Wed, 31 Dec 2014 07:24:23 +0000 (07:24 +0000)]
[X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225037 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes...
Craig Topper [Wed, 31 Dec 2014 07:07:31 +0000 (07:07 +0000)]
[X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225036 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler.
Craig Topper [Wed, 31 Dec 2014 07:07:11 +0000 (07:07 +0000)]
[x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225035 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombine: try to transform A-B < 0 into A < B
David Majnemer [Wed, 31 Dec 2014 04:21:41 +0000 (04:21 +0000)]
InstCombine: try to transform A-B < 0 into A < B

We are allowed to move the 'B' to the right hand side if we an prove
there is no signed overflow and if the comparison itself is signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225034 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "merge consecutive stores of extracted vector elements"
Alexey Samsonov [Wed, 31 Dec 2014 00:40:28 +0000 (00:40 +0000)]
Revert "merge consecutive stores of extracted vector elements"

This reverts commit r224611. This change causes crashes
in X86 DAG->DAG Instruction Selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225031 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword...
Colin LeMahieu [Wed, 31 Dec 2014 00:08:34 +0000 (00:08 +0000)]
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225024 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a test case to not depend on asm comment syntax, so as to be portable
David Blaikie [Tue, 30 Dec 2014 23:33:55 +0000 (23:33 +0000)]
Fix a test case to not depend on asm comment syntax, so as to be portable

Too many different comment characters - instead of trying to account for
them all, instead disable the comments and just check for end-of-line
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225020 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGeneralize even further, for ARM comment syntax (@)
David Blaikie [Tue, 30 Dec 2014 23:23:58 +0000 (23:23 +0000)]
Generalize even further, for ARM comment syntax (@)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225019 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding double-logic on predicate instructions.
Colin LeMahieu [Tue, 30 Dec 2014 23:22:39 +0000 (23:22 +0000)]
[Hexagon] Adding double-logic on predicate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225018 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGeneralize test case to handle different asm syntax (# or // comments)
David Blaikie [Tue, 30 Dec 2014 23:21:57 +0000 (23:21 +0000)]
Generalize test case to handle different asm syntax (# or // comments)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225017 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding newvalue compare and jumps.
Colin LeMahieu [Tue, 30 Dec 2014 23:04:21 +0000 (23:04 +0000)]
[Hexagon] Adding newvalue compare and jumps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225015 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRTDyldMemoryManager.cpp: Make the reference to __morestack weak.
Peter Collingbourne [Tue, 30 Dec 2014 22:52:33 +0000 (22:52 +0000)]
RTDyldMemoryManager.cpp: Make the reference to __morestack weak.

This fixes the DSO build for now. Eventually we should develop some
other mechanism to make this work correctly with DSOs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225014 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDebugInfo: Omit is_stmt from line table entries on the same line.
David Blaikie [Tue, 30 Dec 2014 22:47:13 +0000 (22:47 +0000)]
DebugInfo: Omit is_stmt from line table entries on the same line.

GCC does this for non-zero discriminators and since GCC doesn't produce
column info, that was the only place it comes up there. For LLVM, since
we can emit discriminators and/or column info, it makes more sense to
invert the condition and just test for changes in line number.

This should resolve at least some of the GDB 7.5 test suite failures
created by recent Clang changes that increase the location fidelity
(which, since Clang defaults to including column info on Linux by
default created a bunch of cases that confused GDB).

In theory we could do this better/differently by grouping actual source
statements together in a similar manner to the way lexical scopes are
handled but given that GDB isn't really in a position to consume that (&
users are probably somewhat used to different lines being different
'statements') this seems the safest and cheapest change. (I'm concerned
that doing this 'right' would bloat the debugloc data even further -
something Duncan's working hard to address)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225011 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding postincrement register newvalue stores.
Colin LeMahieu [Tue, 30 Dec 2014 22:34:08 +0000 (22:34 +0000)]
[Hexagon] Adding postincrement register newvalue stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225010 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newva...
Colin LeMahieu [Tue, 30 Dec 2014 22:28:31 +0000 (22:28 +0000)]
[Hexagon] Removing old newvalue store variants.  Adding postincrement immediate newvalue stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225009 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips][microMIPS] Relocate with symbol for micromips symbols
Zoran Jovanovic [Tue, 30 Dec 2014 22:04:16 +0000 (22:04 +0000)]
[mips][microMIPS] Relocate with symbol for micromips symbols
Differential Revision: http://reviews.llvm.org/D6796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225008 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding indexed store new-value variants.
Colin LeMahieu [Tue, 30 Dec 2014 22:00:26 +0000 (22:00 +0000)]
[Hexagon] Adding indexed store new-value variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225007 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding indexed store of immediates.
Colin LeMahieu [Tue, 30 Dec 2014 21:01:38 +0000 (21:01 +0000)]
[Hexagon] Adding indexed store of immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225006 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding indexed stores.
Colin LeMahieu [Tue, 30 Dec 2014 20:42:23 +0000 (20:42 +0000)]
[Hexagon] Adding indexed stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225005 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agox86_64: Fix calls to __morestack under the large code model.
Peter Collingbourne [Tue, 30 Dec 2014 20:05:19 +0000 (20:05 +0000)]
x86_64: Fix calls to __morestack under the large code model.

Under the large code model, we cannot assume that __morestack lives within
2^31 bytes of the call site, so we cannot use pc-relative addressing. We
cannot perform the call via a temporary register, as the rax register may
be used to store the static chain, and all other suitable registers may be
either callee-save or used for parameter passing. We cannot use the stack
at this point either because __morestack manipulates the stack directly.

To avoid these issues, perform an indirect call via a read-only memory
location containing the address.

This solution is not perfect, as it assumes that the .rodata section
is laid out within 2^31 bytes of each function body, but this seems to
be sufficient for JIT.

Differential Revision: http://reviews.llvm.org/D6787

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225003 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] change _sanitizer_cov_module_init to accept int* instead of int**
Kostya Serebryany [Tue, 30 Dec 2014 19:29:28 +0000 (19:29 +0000)]
[asan] change _sanitizer_cov_module_init to accept int* instead of int**

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224999 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[COFF] Don't try to add quotes to already quoted linker directives
Michael Kuperstein [Tue, 30 Dec 2014 19:23:48 +0000 (19:23 +0000)]
[COFF] Don't try to add quotes to already quoted linker directives

If a linker directive is already quoted, don't try to quote it again, otherwise it creates a mess.
This pops up in places like:
#pragma comment(linker,"\"/foo bar'\"")

Differential Revision: http://reviews.llvm.org/D6792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224998 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding reg-reg indexed load forms.
Colin LeMahieu [Tue, 30 Dec 2014 18:58:47 +0000 (18:58 +0000)]
[Hexagon] Adding reg-reg indexed load forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224997 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThe __morestack function is only available on i386 and x86_64 architectures.
Peter Collingbourne [Tue, 30 Dec 2014 18:22:06 +0000 (18:22 +0000)]
The __morestack function is only available on i386 and x86_64 architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224994 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake the __morestack function available to the JIT memory manager under Linux.
Peter Collingbourne [Tue, 30 Dec 2014 18:06:52 +0000 (18:06 +0000)]
Make the __morestack function available to the JIT memory manager under Linux.

This function's implementation lives in libgcc, a static library, so we need
to expose it explicitly, like the other such functions.

Differential Revision: http://reviews.llvm.org/D6788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224993 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Dropping old combine instructions without encodings.
Colin LeMahieu [Tue, 30 Dec 2014 17:53:54 +0000 (17:53 +0000)]
[Hexagon] Dropping old combine instructions without encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224992 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to...
Colin LeMahieu [Tue, 30 Dec 2014 17:39:24 +0000 (17:39 +0000)]
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms.  Adding compare to general register reg-imm form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224991 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Updating constant extender def, adding alu-not instructions, compare to...
Colin LeMahieu [Tue, 30 Dec 2014 15:44:17 +0000 (15:44 +0000)]
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224989 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSome code improvements in Masked Load/Store.
Elena Demikhovsky [Tue, 30 Dec 2014 14:28:14 +0000 (14:28 +0000)]
Some code improvements in Masked Load/Store.
No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224986 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove doesSectionRequireSymbols.
Rafael Espindola [Tue, 30 Dec 2014 13:13:27 +0000 (13:13 +0000)]
Remove doesSectionRequireSymbols.

In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224985 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoreverted prev commit (it was a mistake)
Elena Demikhovsky [Tue, 30 Dec 2014 10:17:21 +0000 (10:17 +0000)]
reverted prev commit (it was a mistake)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224984 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agov
Elena Demikhovsky [Tue, 30 Dec 2014 10:13:38 +0000 (10:13 +0000)]
v

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224983 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd IRBuilder routines for gc.statepoints, gc.results, and gc.relocates
Philip Reames [Tue, 30 Dec 2014 05:55:58 +0000 (05:55 +0000)]
Add IRBuilder routines for gc.statepoints, gc.results, and gc.relocates

Nothing particularly interesting, just adding infrastructure for use by in tree users and out of tree users.

Note: These were extracted out of a working frontend, but they have not been well tested in isolation.

Differential Revision: http://reviews.llvm.org/D6807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224981 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSimplify test a bit.
Rafael Espindola [Tue, 30 Dec 2014 05:09:17 +0000 (05:09 +0000)]
Simplify test a bit.

It looks like the original intent was to check which symbols were created.
With macho-dump the sections were being checked just to match which symbol
was in which section.

llvm-objdump prints the section a symbol is in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224980 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[OCaml] Fix bitrot in tests.
Peter Zotov [Tue, 30 Dec 2014 03:24:14 +0000 (03:24 +0000)]
[OCaml] Fix bitrot in tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224979 91177308-0d34-0410-b5e6-96231b3b80d8