R600/SI: Enable a lot of existing tests for VI (squashed commits)
[oota-llvm.git] / test / CodeGen / R600 /
2015-02-11 Marek OlsakR600/SI: Enable a lot of existing tests for VI (squashe...
2015-02-11 Tom StellardR600/SI: Store immediate offsets > 12-bits in soffset
2015-02-06 Michel DanzerR600/SI: Amend a test to ensure WQM is enabled for...
2015-02-06 Michel DanzerR600/SI: Don't enable WQM for V_INTERP_* instructions v2
2015-02-06 Michel DanzerR600/SI: Also enable WQM for image opcodes which calcul...
2015-02-05 Tom StellardR600/SI: Fix bug in TTI loop unrolling preferences
2015-02-05 Tom StellardR600/SI: Fix bug from insertion of llvm.SI.end.cf into...
2015-02-05 Matt ArsenaultR600/SI: Fix i64 truncate to i1
2015-02-04 Tom StellardR600/SI: Enable subreg liveness by default
2015-02-04 Tom StellardR600/SI: Expand misaligned 16-bit memory accesses
2015-02-04 Tom StellardR600/SI: Make more store operations legal
2015-02-04 Tom StellardR600: Don't promote i64 stores to v2i32 during DAG...
2015-02-03 Marek OlsakR600/SI: Remove the -CHECK suffix from all FileCheck...
2015-02-03 Marek OlsakR600/SI: Fix B64 VALU shifts on VI
2015-02-03 Marek OlsakR600/SI: Don't generate non-existent LSHL, LSHR, ASHR...
2015-02-03 Marek OlsakR600/SI: Fix dependency between instruction writing...
2015-02-02 Tom StellardR600/SI: 64-bit and larger memory access must be at...
2015-02-02 Tom StellardR600/SI: Merge two test files
2015-01-31 Matt ArsenaultR600/SI: Only select cvt_flr/cvt_rpi with no NaNs.
2015-01-29 Matt ArsenaultR600/SI: Implement enableAggressiveFMAFusion
2015-01-29 Tom StellardR600/SI: Define a schedule model and enable the generic...
2015-01-28 Tom StellardR600: Move DataLayout to AMDGPUTargetMachine
2015-01-27 Marek OlsakR600/SI: Enable all tests that pass on VI without changes
2015-01-26 Matt ArsenaultR600: Cleanup or test
2015-01-23 Tom StellardR600/SI: Emit .hsa.version section for amdhsa OS
2015-01-23 Tom StellardR600/SI: Move i64 -> v2i32 load promotion into AMDGPUDA...
2015-01-22 Jan VeselyR600: Try to use lower types for 64bit division if...
2015-01-21 Tim NorthoverDAGCombine: fold (or (and X, M), (and X, N)) -> (and...
2015-01-21 Matt ArsenaultR600: Add checks for urem/srem by a constant
2015-01-21 Matt ArsenaultR600: Add missing tests for i64 srem
2015-01-21 Matt ArsenaultR600/SI: Custom lower fround
2015-01-21 Tim NorthoverRevert "DAGCombine: fold (or (and X, M), (and X, N...
2015-01-21 Tim NorthoverDAGCombine: fold (or (and X, M), (and X, N)) -> (and...
2015-01-20 Tom StellardR600/SI: Fix simple-loop.ll test
2015-01-20 Tom StellardR600/SI: Add kill flag when copying scratch offset...
2015-01-20 Tom StellardR600/SI: Don't store scratch buffer frame index in...
2015-01-18 Matt ArsenaultR600: Remove redundant test
2015-01-16 Matt ArsenaultR600: Clean up floor tests
2015-01-15 Matt ArsenaultR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 Matt ArsenaultR600/SI: Fix trailing comma with modifiers
2015-01-15 Matt ArsenaultR600/SI: Improve fpext / fptrunc test coverage
2015-01-15 Marek OlsakR600/SI: Use 64-bit encoding by default for opcodes...
2015-01-14 Matt ArsenaultR600/SI: Remove some redudant load testcases.
2015-01-14 Matt ArsenaultR600/SI: Fix bad code with unaligned byte vector loads
2015-01-14 Matt ArsenaultImplement new way of expanding extloads.
2015-01-13 Matt ArsenaultR600: Implement getRsqrtEstimate
2015-01-13 Matt ArsenaultR600: Make cttz / ctlz cheap to speculate
2015-01-13 Matt ArsenaultCombine fcmp + select to fminnum / fmaxnum if no nans...
2015-01-12 Tom StellardR600/SI: Use RegisterOperands to specify which operands...
2015-01-08 Tom StellardR600/SI: Remove SIISelLowering::legalizeOperands()
2015-01-07 Matthias BraunRegisterCoalescer: Fix valuesIdentical() in some subran...
2015-01-07 Tom StellardR600/SI: Commute instructions to enable more folding...
2015-01-07 Tom StellardR600/SI: Only fold immediates that have one use
2015-01-07 Tom StellardR600/SI: Add a V_MOV_B64 pseudo instruction
2015-01-07 Tom StellardR600/SI: Teach SIFoldOperands to split 64-bit constants...
2015-01-06 Matt ArsenaultR600/SI: Add combine for isinfinite pattern
2015-01-06 Matt ArsenaultR600/SI: Pattern match isinf to v_cmp_class instructions
2015-01-06 Matt ArsenaultR600/SI: Add basic DAG combines for fp_class
2015-01-06 Matt ArsenaultR600/SI: Add class intrinsic
2015-01-06 Tom StellardR600/SI: Insert s_waitcnt before s_barrier instructions.
2015-01-06 Tom StellardR600/SI: Add a stub GCNTargetMachine
2014-12-21 Matt ArsenaultEnable (sext x) == C --> x == (trunc C) combine
2014-12-19 Matt ArsenaultR600/SI: Only form min/max with 1 use.
2014-12-19 Tom StellardR600/SI: Make sure non-inline constants aren't folded...
2014-12-17 Matt ArsenaultR600/SI: Fix f64 inline immediates
2014-12-15 Duncan P. N. Exon... IR: Make metadata typeless in assembly
2014-12-12 Matt ArsenaultR600: Fix min/max matching problems with unordered...
2014-12-12 Matt ArsenaultR600/SI: Don't promote f32 select to i32
2014-12-12 Matt ArsenaultAdd target hook for whether it is profitable to reduce...
2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
2014-12-08 Tom StellardMISched: Fix moving stores across barriers
2014-12-06 Tom StellardR600/SI: Restore PrivateGlobalPrefix to the default...
2014-12-03 Matt ArsenaultR600/SI: Remove i1 pseudo VALU ops
2014-12-03 Tom StellardR600/SI: Enable inline assembly
2014-12-03 Matt ArsenaultR600/SI: Change mubuf offsets to print as decimal
2014-12-02 Tom StellardR600/SI: Move more information into SIProgramInfo struct
2014-12-02 Matt ArsenaultR600: Cleanup some tests and add missing testcases
2014-12-02 Tom StellardR600/SI: Set the ATC bit on all resource descriptors...
2014-11-28 Matt ArsenaultR600/SI: Fix assertion on sign extend of 3 vectors
2014-11-23 Matt ArsenaultR600: Fix extloads of i1 on R600/Evergreen
2014-11-23 Matt ArsenaultR600/SI: Add additional tests for i1 loads
2014-11-23 Matt ArsenaultR600/SI: Fix broken check lines and modernize prefixes
2014-11-23 Matt ArsenaultR600/SI: Fix missing -verify-machineinstrs on a test
2014-11-21 Tom StellardR600/SI: Add a failing test case for offset order in...
2014-11-21 Tom StellardR600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
2014-11-21 Tom StellardR600/SI: Add SIFoldOperands pass
2014-11-21 Tom StellardR600/SI: Use hex notation for constant in test
2014-11-19 Tom StellardR600/SI: Make SIInstrInfo::isOperandLegal() more strict
2014-11-19 Matt ArsenaultR600/SI: Implement areMemAccessesTriviallyDisjoint
2014-11-18 Matt ArsenaultR600/SI: Move SIFixSGPRCopies to inst selector passes
2014-11-18 Tom StellardR600/SI: Make sure resource descriptors are always...
2014-11-15 Matt ArsenaultR600: Permute operands when selecting legacy min/max
2014-11-14 Tom StellardR600/SI: Fix spilling of m0 register
2014-11-14 Matt ArsenaultR600/SI: Combine min3/max3 instructions
2014-11-14 Matt ArsenaultR600/SI: Fix verifier error from a branch on IMPLICIT_DEF
2014-11-14 Matt ArsenaultR600/SI: Match integer min / max instructions
2014-11-14 Matt ArsenaultR600/SI: Use S_BFE_I64 for 64-bit sext_inreg
2014-11-13 Matt ArsenaultR600/SI: Fix fmin_legacy / fmax_legacy matching for SI
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