Allow a target to create a null streamer.
[oota-llvm.git] / test / CodeGen / R600 /
2014-06-19 Matt ArsenaultR600: Add a few tests I forgot to add.
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Matt ArsenaultR600: Handle fnearbyint
2014-06-18 Marek OlsakR600/SI: add gather4 and getlod intrinsics (v3)
2014-06-18 Jan VeselyR600: Expand vector fceil
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600/SI: Prettier operand printing for 64-bit ops.
2014-06-18 Matt ArsenaultR600: Implement f64 ftrunc, ffloor and fceil.
2014-06-18 Matt ArsenaultR600: Custom lower f64 frint for pre-CI
2014-06-18 Jan VeselyR600: Implement 64bit SRA
2014-06-18 Jan VeselyR600: Implement 64bit SRL
2014-06-18 Jan VeselyR600: Implement 64bit SHL
2014-06-17 Matt ArsenaultR600/SI: Match cttz_zero_undef
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32
2014-06-15 Matt ArsenaultR600: Add a rotr testcase I forgot to add
2014-06-15 Matt ArsenaultR600: Remove a few more things from AMDILISelLowering
2014-06-15 Matt ArsenaultR600: Fix assert on vector sdiv
2014-06-15 Matt ArsenaultR600: Report that integer division is expensive.
2014-06-15 NAKAMURA TakumiDon't expect tests always crashing. Add "REQUIRES:asserts".
2014-06-14 Matt ArsenaultR600: Add failing testcases.
2014-06-14 Matt ArsenaultR600: Fix asserts related to constant initializers
2014-06-13 Tim NorthoverIR: add "cmpxchg weak" variant to support permitted...
2014-06-13 Matt ArsenaultR600/SI: Fix selection error on i64 rotl / rotr.
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-12 Tom StellardRevert "SelectionDAG: Enable (and (setcc x), (setcc...
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-09 Alp TokerReduce verbiage of lit.local.cfg files
2014-06-09 Matt ArsenaultR600/SI: Keep 64-bit not on SALU
2014-06-09 Matt ArsenaultR600: Fix selection failure for vector bswap
2014-06-09 Matt ArsenaultR600: Add more and testcases
2014-06-06 Rafael EspindolaAllow aliases to be unnamed_addr.
2014-06-05 Matt ArsenaultR600: Fix test. Using wrong check prefix.
2014-06-05 Matt ArsenaultR600/SI: Match rsq instructions
2014-05-31 Matt ArsenaultR600/SI: Fix [s|u]int_to_fp for i1
2014-05-22 Matt ArsenaultR600: Try to convert BFE back to standard bit ops when...
2014-05-22 Matt ArsenaultR600: Add dag combine for BFE
2014-05-22 Matt ArsenaultR600: Implement ComputeNumSignBitsForTargetNode for BFE
2014-05-22 Matt ArsenaultR600: Expand mul24 for GPUs without it
2014-05-22 Matt ArsenaultR600: Expand mad24 for GPUs without it
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24
2014-05-22 Matt ArsenaultR600/SI: Match fp_to_uint / uint_to_fp for f64
2014-05-21 Matt ArsenaultR600: Partially fix constant initializers for structs...
2014-05-21 Matt ArsenaultR600: Add failing testcases for constant initializers.
2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
2014-05-15 Tom StellardR600/SI: Only use SALU instructions for 64-bit add...
2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
2014-05-14 Jay FoadRename ComputeMaskedBits to computeKnownBits. "Masked...
2014-05-13 Matt ArsenaultR600/SI: Try to fix BFE operands when moving to VALU
2014-05-12 Matt ArsenaultR600: Add mul24 intrinsics
2014-05-12 Matt ArsenaultMake SimplifyDemandedBits understand BUILD_PAIR
2014-05-10 Vincent LejeuneR600/SI: Fold fabs/fneg into src input modifier
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
2014-05-09 Tom StellardR600/SI: Teach SIInstrInfo::moveToVALU() how to move...
2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
2014-05-09 Tom StellardR600: Expand i64 SELECT_CC
2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
2014-05-05 Tom StellardR600: Expand i64 ISD:SUB
2014-05-02 Tom StellardR600: Expand vector sin and cos.
2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8}
2014-05-01 Matt ArsenaultR600/SI: Fix verifier error with pseudo store instructions.
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-30 Tom StellardR600/SI: Teach moveToVALU how to handle some SMRD instr...
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
2014-04-23 Matt ArsenaultR600: Add a test that used to be broken that I forgot...
2014-04-22 Matt ArsenaultR600: Emit error instead of unreachable on function...
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-18 Matt ArsenaultR600/SI: Try to use scalar BFE.
2014-04-18 Matt ArsenaultR600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
2014-04-18 Tom StellardR600/SI: Use SReg_64 instead of VSrc_64 when selecting...
2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
2014-04-17 Matt ArsenaultR600/SI: f64 frint is legal on CI
2014-04-17 Matt ArsenaultR600/SI: Fix zext from i1 to i64
2014-04-16 Matt ArsenaultR600: Extend r600 sign_extend_inreg tests for EG
2014-04-15 Matt ArsenaultR600/SI: Print more immediates in hex format
2014-04-15 Matt ArsenaultR600/SI: Fix loads of i1
2014-04-11 Tom StellardSelectionDAG: Use helper function to improve legalizati...
2014-04-09 Matt ArsenaultR600/SI: Match not instruction.
2014-04-07 Tom StellardR600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
2014-04-03 Tom StellardR600: Correct opcode for BFE_INT
2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
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