[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...
[oota-llvm.git] / test / CodeGen / Mips / msa / bitwise.ll
2013-09-27 Daniel Sanders[mips][msa] MSA requires FR=1 mode (64-bit FPU register...
2013-09-24 Daniel Sanders[mips][msa] Added support for matching andi, ori, nori...
2013-09-24 Daniel Sanders[mips][msa] Added support for matching slli, srai,...
2013-09-23 Daniel Sanders[mips][msa] Added support for matching pcnt from normal...
2013-09-23 Daniel Sanders[mips][msa] Added support for matching nor from normal...
2013-09-23 Daniel Sanders[mips][msa] Added support for matching and, or, and...
2013-09-11 Daniel Sanders[mips][msa] Added test cases that were supposed to...