Remove extraneous includes from the target machines.
[oota-llvm.git] / lib / Target / R600 /
2014-06-26 Matt ArsenaultR600/SI: Add FP mode bits to binary.
2014-06-26 Aaron BallmanSilencing a warning about isZExtFree hiding an inherite...
2014-06-26 Matt ArsenaultR600: Fix vector FMA
2014-06-24 Tom StellardR600/SI: Use a ComplexPattern for MUBUF stores
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600: Remove DIV_INF
2014-06-24 Matt ArsenaultR600/SI: Move pattern to instruction definition
2014-06-23 Matt ArsenaultR600/SI: Verify restrictions on div_scale operands.
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-23 Matt ArsenaultR600: Remove AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Select is not expensive.
2014-06-23 Matt ArsenaultR600: Move add/sub with overflow out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Move more out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Don't set fp_round_inreg action.
2014-06-23 Matt ArsenaultR600/SI: Handle i64 sub.
2014-06-23 Matt ArsenaultR600/SI: Move selection of i64 add to separate function.
2014-06-23 Matt ArsenaultR600: Rename AMDIL file
2014-06-23 Matt ArsenaultFix missing words in sentence
2014-06-23 Matt ArsenaultUse helper function
2014-06-23 Matt ArsenaultAlphabetize forward declarations
2014-06-22 Jan VeselyR600: Use LowerSDIVREM for i64 node replace
2014-06-22 Jan VeselyR600: Implement custom SDIVREM.
2014-06-20 Tom StellardR600/SI: Add patterns for ctpop inside a branch
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600: Expand vector flog2
2014-06-20 Tom StellardR600: Expand vector fexp2
2014-06-20 Tom StellardR600/SI: SI Control Flow Annotation bug fixed
2014-06-20 Tom StellardR600/SI: Add a VALU pattern for i64 xor
2014-06-20 Matt ArsenaultR600: Trivial subtarget feature cleanups.
2014-06-19 Alp TokerFix typos
2014-06-19 Craig TopperConvert some assert(0) to llvm_unreachable or fold...
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Matt ArsenaultUse stdint macros for specifying size of constants
2014-06-18 Matt ArsenaultR600: Handle fnearbyint
2014-06-18 Marek OlsakR600/SI: add gather4 and getlod intrinsics (v3)
2014-06-18 Matt ArsenaultUse LL suffix for literal that should be 64-bits.
2014-06-18 Jan VeselyR600: Expand vector fceil
2014-06-18 Matt ArsenaultWork around ridiculous warning.
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600/SI: Prettier operand printing for 64-bit ops.
2014-06-18 Matt ArsenaultR600: Implement f64 ftrunc, ffloor and fceil.
2014-06-18 Matt ArsenaultR600: Custom lower f64 frint for pre-CI
2014-06-18 Matt ArsenaultR600/SI: Temporary fix for f64 fneg
2014-06-18 Matt ArsenaultR600/SI: Comparisons set vcc.
2014-06-18 Jan VeselyR600: Implement 64bit SRA
2014-06-18 Jan VeselyR600: Implement 64bit SRL
2014-06-18 Jan VeselyR600: Implement 64bit SHL
2014-06-17 Tom StellardR600/SI: Make sure target flags are set on pseudo VOP3...
2014-06-17 Matt ArsenaultR600/SI: Match cttz_zero_undef
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardR600/SI: Add a pattern for llvm.AMDGPU.barrier.global
2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32
2014-06-17 Tom StellardR600/SI: Re-initialize the m0 register after using...
2014-06-15 Matt ArsenaultFix copy paste error
2014-06-15 Matt ArsenaultR600: Remove a few more things from AMDILISelLowering
2014-06-15 Matt ArsenaultR600: Fix assert on vector sdiv
2014-06-15 Matt ArsenaultR600: Move / cleanup more leftover AMDIL stuff.
2014-06-15 Matt ArsenaultR600: Move division custom lowering out of AMDILISelLow...
2014-06-15 Matt ArsenaultR600: Report that integer division is expensive.
2014-06-15 Matt ArsenaultR600: Remove dead code
2014-06-14 Matt ArsenaultFix typo
2014-06-14 Matt ArsenaultR600: Fix asserts related to constant initializers
2014-06-14 Matt ArsenaultR600: Use address space enum instead of value
2014-06-13 Matt ArsenaultR600: Cleanup some old AMDIL stuff.
2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
2014-06-13 Matt ArsenaultR600: Don't call setOperationAction with things that...
2014-06-13 Matt ArsenaultR600/SI: Fix selection error on i64 rotl / rotr.
2014-06-13 Tom StellardR600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in R600InstrInfo.cpp
2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in AMDGPUInstrIn...
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Tom StellardR600: Set correct InstrItinClass for instructions using...
2014-06-11 Tom StellardR600: BCNT_INT is a vector only instruction
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Update place using old subtarget predicate
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for 64-bit LDS...
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for more LDS ops
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-11 Rafael EspindolaTry to fix the msvc build.
2014-06-11 Matt ArsenaultUse cast instead of assert + dyn_cast
2014-06-11 Matt ArsenaultR600: Add helper functions.
2014-06-10 Tom StellardR600/SI: Emit an error when attempting to spill VGPRs v4
2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-09 Matt ArsenaultR600/SI: Rename VOP3 helper class to be more general
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