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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
lib
/
Target
/
R600
/ SILoadStoreOptimizer.cpp
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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commitdiff
2015-05-12
Tom Stellard
R600/SI: Remove explicit m0 operand from DS instructions
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commitdiff
2015-03-23
Benjamin Kramer
Re-sort includes with sort-includes.py and insert raw_o...
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2015-03-09
Tom Stellard
R600/SI: Move gds operand to the end of operand list
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commitdiff
2015-01-30
Eric Christopher
Reuse a bunch of cached subtargets and remove getSubtar...
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2014-12-03
Matt Arsenault
R600/SI: Fix live range error hidden by SIFoldOperands
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2014-11-21
Tom Stellard
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
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2014-10-31
Reid Kleckner
Work around bugs in MSVC "14" CTP 3's conversion logic
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commitdiff
2014-10-10
Matt Arsenault
R600/SI: Match read2/write2 stride 64 versions
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commitdiff
2014-10-10
Matt Arsenault
R600/SI: Add load / store machine optimizer pass.
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