Don't reach into the middle of TargetMachine and cache one of its ivars.
[oota-llvm.git] / lib / Target / R600 / AMDILISelDAGToDAG.cpp
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 2/4.
2013-05-23 Benjamin KramerMove passes from namespace llvm into anonymous namespac...
2013-04-19 Michael LiaoArrayRefize getMachineNode(). No functionality change.
2013-04-05 Tom StellardR600/SI: Add support for buffer stores v2
2013-03-14 Vincent LejeuneR600: Factorize code handling Const Read Port limitation
2013-03-05 Vincent LejeuneR600: Turn BUILD_VECTOR into Reg_Sequence
2013-02-26 Christian KonigR600/SI: add post ISel folding for SI v2
2013-02-26 Christian KonigR600/SI: add folding helper
2013-02-14 Vincent LejeuneR600: Do not fold single instruction with more that...
2013-02-14 Vincent LejeuneR600: Do not fold modifier/litterals in vector inst
2013-02-07 Tom StellardR600/SI: simplify and fix SMRD encoding
2013-02-06 Tom StellardR600: Support for indirect addressing v4
2013-01-31 Tom StellardR600: Fold clamp, neg, abs
2013-01-31 Tom StellardR600: Consider bitcast when folding const_address node.
2013-01-23 Tom StellardR600: rework handling of the constants
2012-12-11 Tom StellardAdd R600 backend