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With -neon-reg-sequence, models forming a Q register from a pair of consecutive D...
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
Thumb1RegisterInfo.h
2010-03-09
Jim Grosbach
Change the Value argument to eliminateFrameIndex to...
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2009-11-07
Jim Grosbach
80-column cleanup of file header comments
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2009-10-28
Jim Grosbach
Cleanup now that frame index scavenging via post-pass...
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2009-10-21
Jim Grosbach
Missing piece of the ARM frame index post-scavenging...
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2009-10-20
Jim Grosbach
Now that all ARM subtargets use frame index scavenging...
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2009-10-19
Jim Grosbach
Adjust the scavenge register spilling to allow the...
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2009-10-08
Jim Grosbach
Re-enable register scavenging in Thumb1 by default.
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2009-10-07
Jim Grosbach
reverting thumb1 scavenging default due to test failure...
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2009-10-07
Jim Grosbach
Enable thumb1 register scavenging by default.
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2009-10-07
Jim Grosbach
Add register-reuse to frame-index register scavenging...
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2009-10-05
Jim Grosbach
In Thumb1, the register scavenger is not always able...
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2009-08-11
Owen Anderson
Split EVT into MVT and EVT, the former representing...
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2009-08-10
Owen Anderson
Rename MVT to EVT, in preparation for splitting SimpleV...
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2009-07-28
Evan Cheng
- More refactoring. This gets rid of all of the getOpco...
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2009-07-26
Evan Cheng
Refactor. Get rid of a few more getOpcode() calls.
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2009-07-24
David Goodwin
Correctly handle the Thumb-2 imm8 addrmode. Specialize...
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2009-07-16
Evan Cheng
Let callers decide the sub-register index on the def...
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2009-07-08
David Goodwin
Generalize opcode selection in ARMBaseRegisterInfo.
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2009-07-08
David Goodwin
Push methods into base class in preparation for sharing.
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2009-07-02
David Goodwin
Checkpoint refactoring of ThumbInstrInfo and ThumbRegis...
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