0x1f0c2517, 0x1f261440
};
-int rk3288_vpu_h264d_init(struct rk3288_vpu_ctx *ctx)
+int rk3288_vpu_h264d_init(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
int ret;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.h264d.priv_tbl,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.h264d.priv_tbl,
sizeof(struct rk3288_vpu_h264d_priv_tbl));
if (ret) {
vpu_err("allocate h264 priv_tbl failed\n");
return 0;
}
-void rk3288_vpu_h264d_exit(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_h264d_exit(struct rockchip_vpu_ctx *ctx)
{
- rk3288_vpu_aux_buf_free(ctx->dev, &ctx->hw.h264d.priv_tbl);
+ rockchip_vpu_aux_buf_free(ctx->dev, &ctx->hw.h264d.priv_tbl);
}
-static void rk3288_vpu_h264d_prepare_table(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_h264d_prepare_table(struct rockchip_vpu_ctx *ctx)
{
struct rk3288_vpu_h264d_priv_tbl *tbl = ctx->hw.h264d.priv_tbl.cpu;
const struct v4l2_ctrl_h264_scaling_matrix *scaling =
memcpy(tbl->scaling_list, scaling, sizeof(tbl->scaling_list));
}
-static void rk3288_vpu_h264d_set_params(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_h264d_set_params(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_h264_decode_param *dec_param =
ctx->run.h264d.decode_param;
ctx->run.h264d.slice_param;
const struct v4l2_ctrl_h264_sps *sps = ctx->run.h264d.sps;
const struct v4l2_ctrl_h264_pps *pps = ctx->run.h264d.pps;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 reg;
/* Decoder control register 0. */
}
-static void rk3288_vpu_h264d_set_ref(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_h264d_set_ref(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_h264_decode_param *dec_param =
ctx->run.h264d.decode_param;
const struct v4l2_h264_dpb_entry *dpb = ctx->run.h264d.dpb;
const u8 *dpb_map = ctx->run.h264d.dpb_map;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 dpb_longterm = 0;
u32 dpb_valid = 0;
int reg_num;
}
}
-static void rk3288_vpu_h264d_set_buffers(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_h264d_set_buffers(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_h264_sps *sps = ctx->run.h264d.sps;
const struct v4l2_ctrl_h264_slice_param *slice =
ctx->run.h264d.slice_param;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
dma_addr_t src_dma, dst_dma;
/* Source (stream) buffer. */
VDPU_REG_ADDR_QTABLE);
}
-void rk3288_vpu_h264d_run(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_h264d_run(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
/* Prepare data in memory. */
rk3288_vpu_h264d_prepare_table(ctx);
- rk3288_vpu_power_on(vpu);
+ rockchip_vpu_power_on(vpu);
/* Configure hardware registers. */
rk3288_vpu_h264d_set_params(ctx);
{ 0, -1, 12, 123, -6, 0 }
};
-static inline void vp8d_reg_write(struct rk3288_vpu_dev *vpu,
+static inline void vp8d_reg_write(struct rockchip_vpu_dev *vpu,
const struct vp8d_reg *reg, u32 val)
{
u32 v;
/* dump hw params for debug */
#ifdef DEBUG
-static void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_dump_hdr(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
int dct_total_len = 0;
vpu_debug(4, "Dct Part Total Length: 0x%x\n", dct_total_len);
}
#else
-static inline void rk3288_vp8d_dump_hdr(struct rk3288_vpu_ctx *ctx) {}
+static inline void rk3288_vp8d_dump_hdr(struct rockchip_vpu_ctx *ctx) {}
#endif
-static void rk3288_vp8d_prob_update(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_prob_update(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
const struct v4l2_vp8_entropy_hdr *entropy_hdr = &hdr->entropy_hdr;
/*
* set loop filters
*/
-static void rk3288_vp8d_cfg_lf(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_lf(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 reg;
int i;
/*
* set quantization parameters
*/
-static void rk3288_vp8d_cfg_qp(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_qp(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
int i;
if (!(hdr->sgmnt_hdr.flags & V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED)) {
* 3. number of dct parts is 1, 2, 4 or 8
* 4. the addresses set to vpu must be 64bits alignment
*/
-static void rk3288_vp8d_cfg_parts(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_parts(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 dct_part_total_len = 0;
u32 dct_size_part_size = 0;
u32 dct_part_offset = 0;
* prediction filter taps
* normal 6-tap filters
*/
-static void rk3288_vp8d_cfg_tap(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_tap(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
struct vp8d_reg reg;
u32 val = 0;
int i, j;
}
/* set reference frame */
-static void rk3288_vp8d_cfg_ref(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_ref(struct rockchip_vpu_ctx *ctx)
{
u32 reg;
struct vb2_buffer *buf;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
/* set last frame address */
vdpu_write_relaxed(vpu, reg, VDPU_REG_ADDR_REF(5));
}
-static void rk3288_vp8d_cfg_buffers(struct rk3288_vpu_ctx *ctx)
+static void rk3288_vp8d_cfg_buffers(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 reg;
/* set probability table buffer address */
VDPU_REG_ADDR_DST);
}
-int rk3288_vpu_vp8d_init(struct rk3288_vpu_ctx *ctx)
+int rk3288_vpu_vp8d_init(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
unsigned int mb_width, mb_height;
size_t segment_map_size;
int ret;
* In context init the dma buffer for segment map must be allocated.
* And the data in segment map buffer must be set to all zero.
*/
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.segment_map,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.segment_map,
segment_map_size);
if (ret) {
vpu_err("allocate segment map mem failed\n");
* Allocate probability table buffer,
* total 1208 bytes, 4K page is far enough.
*/
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.prob_tbl,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8d.prob_tbl,
sizeof(struct vp8_prob_tbl_packed));
if (ret) {
vpu_err("allocate prob table mem failed\n");
return 0;
prob_table_failed:
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
return ret;
}
-void rk3288_vpu_vp8d_exit(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8d_exit(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.prob_tbl);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.segment_map);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8d.prob_tbl);
}
-void rk3288_vpu_vp8d_run(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8d_run(struct rockchip_vpu_ctx *ctx)
{
const struct v4l2_ctrl_vp8_frame_hdr *hdr = ctx->run.vp8d.frame_hdr;
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
size_t height = ctx->dst_fmt.height;
size_t width = ctx->dst_fmt.width;
u32 mb_width, mb_height;
rk3288_vp8d_prob_update(ctx);
- rk3288_vpu_power_on(vpu);
+ rockchip_vpu_power_on(vpu);
reg = VDPU_REG_CONFIG_DEC_TIMEOUT_E
| VDPU_REG_CONFIG_DEC_STRENDIAN_E
* Required buffer layout:
* |<--hdr-->|<--ext hdr-->|<---dct part---
*/
-void rk3288_vpu_vp8e_assemble_bitstream(struct rk3288_vpu_ctx *ctx,
- struct rk3288_vpu_buf *dst_buf)
+void rk3288_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
+ struct rockchip_vpu_buf *dst_buf)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&dst_buf->vb.vb2_buf);
size_t ext_hdr_size = dst_buf->vp8e.ext_hdr_size;
return round_up(w, MB_DIM) * round_up(h, MB_DIM);
}
-int rk3288_vpu_vp8e_init(struct rk3288_vpu_ctx *ctx)
+int rk3288_vpu_vp8e_init(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
size_t height = ctx->src_fmt.height;
size_t width = ctx->src_fmt.width;
size_t ref_buf_size;
size_t mv_size;
int ret;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
if (ret) {
vpu_err("failed to allocate ctrl buffer\n");
}
mv_size = DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16) / 4;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
if (ret) {
vpu_err("failed to allocate MV buffer\n");
goto err_ctrl_buf;
}
ref_buf_size = ref_luma_size(width, height) * 3 / 2;
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
2 * ref_buf_size);
if (ret) {
vpu_err("failed to allocate ext buffer\n");
return 0;
err_mv_buf:
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
err_ctrl_buf:
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
return ret;
}
-void rk3288_vpu_vp8e_exit(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
- rk3288_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
}
-static inline u32 enc_in_img_ctrl(struct rk3288_vpu_ctx *ctx)
+static inline u32 enc_in_img_ctrl(struct rockchip_vpu_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
struct v4l2_rect *crop = &ctx->src_crop;
| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
}
-static void rk3288_vpu_vp8e_set_buffers(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_vp8e_set_buffers(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
- const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
+ const struct rk3288_vp8e_reg_params *params =
+ (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
dma_addr_t ref_buf_dma, rec_buf_dma;
dma_addr_t stream_dma;
size_t rounded_size;
rec_buf_dma += rounded_size * 3 / 2;
ctx->hw.vp8e.ref_rec_ptr ^= 1;
- if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
dst_dma = vpu->dummy_encode_dst.dma;
dst_size = vpu->dummy_encode_dst.size;
} else {
VEPU_REG_ADDR_REC_CHROMA);
/* Source buffer. */
- if (rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_Y].dma,
VEPU_REG_ADDR_IN_LUMA);
vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CB].dma,
vepu_write_relaxed(vpu, enc_in_img_ctrl(ctx), VEPU_REG_IN_IMG_CTRL);
}
-static void rk3288_vpu_vp8e_set_params(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_ctx *ctx)
+static void rk3288_vpu_vp8e_set_params(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_ctx *ctx)
{
- const struct rk3288_vp8e_reg_params *params = ctx->run.vp8e.reg_params;
+ const struct rk3288_vp8e_reg_params *params =
+ (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
int i;
vepu_write_relaxed(vpu, params->enc_ctrl0, VEPU_REG_ENC_CTRL0);
VEPU_REG_VP8_LOOP_FLT_DELTA(i));
}
-void rk3288_vpu_vp8e_run(struct rk3288_vpu_ctx *ctx)
+void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
u32 reg;
/* The hardware expects the control buffer to be zeroed. */
/*
* Program the hardware.
*/
- rk3288_vpu_power_on(vpu);
+ rockchip_vpu_power_on(vpu);
vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_VP8,
VEPU_REG_ENC_CTRL);
vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
}
-void rk3288_vpu_vp8e_done(struct rk3288_vpu_ctx *ctx,
+void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result)
{
struct rk3288_vpu_vp8e_ctrl_buf *ctrl_buf = ctx->hw.vp8e.ctrl_buf.cpu;
ctx->run.dst->vp8e.ext_hdr_size = ctrl_buf->ext_hdr_size;
ctx->run.dst->vp8e.dct_size = ctrl_buf->dct_size;
- rk3288_vpu_run_done(ctx, result);
+ rockchip_vpu_run_done(ctx, result);
}
/*
* WAR for encoder state corruption after decoding
*/
-static const struct rk3288_vp8e_reg_params dummy_encode_reg_params = {
- /* 00000014 */ .hdr_len = 0x00000000,
- /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
- /* 00000040 */ .enc_ctrl0 = 0x00000000,
- /* 00000044 */ .enc_ctrl1 = 0x00000000,
- /* 00000048 */ .enc_ctrl2 = 0x00040014,
- /* 0000004c */ .enc_ctrl3 = 0x404083c0,
- /* 00000050 */ .enc_ctrl5 = 0x01006bff,
- /* 00000054 */ .enc_ctrl4 = 0x00000039,
- /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
- /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
- /* 00000064 */ .mad_ctrl = 0x00000000,
- /* 0000006c */ .qp_val = {
- /* 0000006c */ 0x020213b1,
- /* 00000070 */ 0x02825249,
- /* 00000074 */ 0x048409d8,
- /* 00000078 */ 0x03834c30,
- /* 0000007c */ 0x020213b1,
- /* 00000080 */ 0x02825249,
- /* 00000084 */ 0x00340e0d,
- /* 00000088 */ 0x401c1a15,
+static const struct rockchip_reg_params dummy_encode_reg_params = {
+ .rk3288_vp8e = {
+ /* 00000014 */ .hdr_len = 0x00000000,
+ /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
+ /* 00000040 */ .enc_ctrl0 = 0x00000000,
+ /* 00000044 */ .enc_ctrl1 = 0x00000000,
+ /* 00000048 */ .enc_ctrl2 = 0x00040014,
+ /* 0000004c */ .enc_ctrl3 = 0x404083c0,
+ /* 00000050 */ .enc_ctrl5 = 0x01006bff,
+ /* 00000054 */ .enc_ctrl4 = 0x00000039,
+ /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
+ /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
+ /* 00000064 */ .mad_ctrl = 0x00000000,
+ /* 0000006c */ .qp_val = {
+ /* 0000006c */ 0x020213b1,
+ /* 00000070 */ 0x02825249,
+ /* 00000074 */ 0x048409d8,
+ /* 00000078 */ 0x03834c30,
+ /* 0000007c */ 0x020213b1,
+ /* 00000080 */ 0x02825249,
+ /* 00000084 */ 0x00340e0d,
+ /* 00000088 */ 0x401c1a15,
+ },
+ /* 0000008c */ .bool_enc = 0x00018140,
+ /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
+ /* 00000094 */ .rlc_ctrl = 0x14000000,
+ /* 00000098 */ .mb_ctrl = 0x00000000,
+ /* 000000d4 */ .rgb_yuv_coeff = {
+ /* 000000d4 */ 0x962b4c85,
+ /* 000000d8 */ 0x90901d50,
+ },
+ /* 000000dc */ .rgb_mask_msb = 0x0000b694,
+ /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
+ /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
+ /* 000000f0 */ .first_roi_area = 0xffffffff,
+ /* 000000f4 */ .second_roi_area = 0xffffffff,
+ /* 000000f8 */ .mvc_ctrl = 0x01780000,
+ /* 00000100 */ .intra_penalty = {
+ /* 00000100 */ 0x00010005,
+ /* 00000104 */ 0x00015011,
+ /* 00000108 */ 0x0000c005,
+ /* 0000010c */ 0x00016010,
+ /* 00000110 */ 0x0001a018,
+ /* 00000114 */ 0x00018015,
+ /* 00000118 */ 0x0001d01a,
+ },
+ /* 00000120 */ .seg_qp = {
+ /* 00000120 */ 0x020213b1,
+ /* 00000124 */ 0x02825249,
+ /* 00000128 */ 0x048409d8,
+ /* 0000012c */ 0x03834c30,
+ /* 00000130 */ 0x020213b1,
+ /* 00000134 */ 0x02825249,
+ /* 00000138 */ 0x00340e0d,
+ /* 0000013c */ 0x341c1a15,
+ /* 00000140 */ 0x020213b1,
+ /* 00000144 */ 0x02825249,
+ /* 00000148 */ 0x048409d8,
+ /* 0000014c */ 0x03834c30,
+ /* 00000150 */ 0x020213b1,
+ /* 00000154 */ 0x02825249,
+ /* 00000158 */ 0x00340e0d,
+ /* 0000015c */ 0x341c1a15,
+ /* 00000160 */ 0x020213b1,
+ /* 00000164 */ 0x02825249,
+ /* 00000168 */ 0x048409d8,
+ /* 0000016c */ 0x03834c30,
+ /* 00000170 */ 0x020213b1,
+ /* 00000174 */ 0x02825249,
+ /* 00000178 */ 0x00340e0d,
+ /* 0000017c */ 0x341c1a15,
+ },
+ /* 00000180 */ .dmv_4p_1p_penalty = {
+ /* 00000180 */ 0x00020406,
+ /* 00000184 */ 0x080a0c0e,
+ /* 00000188 */ 0x10121416,
+ /* 0000018c */ 0x181a1c1e,
+ /* 00000190 */ 0x20222426,
+ /* 00000194 */ 0x282a2c2e,
+ /* 00000198 */ 0x30323436,
+ /* 0000019c */ 0x383a3c3e,
+ /* 000001a0 */ 0x40424446,
+ /* 000001a4 */ 0x484a4c4e,
+ /* 000001a8 */ 0x50525456,
+ /* 000001ac */ 0x585a5c5e,
+ /* 000001b0 */ 0x60626466,
+ /* 000001b4 */ 0x686a6c6e,
+ /* 000001b8 */ 0x70727476,
+ /* NOTE: Further 17 registers set to 0. */
+ },
+ /*
+ * NOTE: Following registers all set to 0:
+ * - dmv_qpel_penalty,
+ * - vp8_ctrl1,
+ * - bit_cost_golden,
+ * - loop_flt_delta.
+ */
},
- /* 0000008c */ .bool_enc = 0x00018140,
- /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
- /* 00000094 */ .rlc_ctrl = 0x14000000,
- /* 00000098 */ .mb_ctrl = 0x00000000,
- /* 000000d4 */ .rgb_yuv_coeff = {
- /* 000000d4 */ 0x962b4c85,
- /* 000000d8 */ 0x90901d50,
- },
- /* 000000dc */ .rgb_mask_msb = 0x0000b694,
- /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
- /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
- /* 000000f0 */ .first_roi_area = 0xffffffff,
- /* 000000f4 */ .second_roi_area = 0xffffffff,
- /* 000000f8 */ .mvc_ctrl = 0x01780000,
- /* 00000100 */ .intra_penalty = {
- /* 00000100 */ 0x00010005,
- /* 00000104 */ 0x00015011,
- /* 00000108 */ 0x0000c005,
- /* 0000010c */ 0x00016010,
- /* 00000110 */ 0x0001a018,
- /* 00000114 */ 0x00018015,
- /* 00000118 */ 0x0001d01a,
- },
- /* 00000120 */ .seg_qp = {
- /* 00000120 */ 0x020213b1,
- /* 00000124 */ 0x02825249,
- /* 00000128 */ 0x048409d8,
- /* 0000012c */ 0x03834c30,
- /* 00000130 */ 0x020213b1,
- /* 00000134 */ 0x02825249,
- /* 00000138 */ 0x00340e0d,
- /* 0000013c */ 0x341c1a15,
- /* 00000140 */ 0x020213b1,
- /* 00000144 */ 0x02825249,
- /* 00000148 */ 0x048409d8,
- /* 0000014c */ 0x03834c30,
- /* 00000150 */ 0x020213b1,
- /* 00000154 */ 0x02825249,
- /* 00000158 */ 0x00340e0d,
- /* 0000015c */ 0x341c1a15,
- /* 00000160 */ 0x020213b1,
- /* 00000164 */ 0x02825249,
- /* 00000168 */ 0x048409d8,
- /* 0000016c */ 0x03834c30,
- /* 00000170 */ 0x020213b1,
- /* 00000174 */ 0x02825249,
- /* 00000178 */ 0x00340e0d,
- /* 0000017c */ 0x341c1a15,
- },
- /* 00000180 */ .dmv_4p_1p_penalty = {
- /* 00000180 */ 0x00020406,
- /* 00000184 */ 0x080a0c0e,
- /* 00000188 */ 0x10121416,
- /* 0000018c */ 0x181a1c1e,
- /* 00000190 */ 0x20222426,
- /* 00000194 */ 0x282a2c2e,
- /* 00000198 */ 0x30323436,
- /* 0000019c */ 0x383a3c3e,
- /* 000001a0 */ 0x40424446,
- /* 000001a4 */ 0x484a4c4e,
- /* 000001a8 */ 0x50525456,
- /* 000001ac */ 0x585a5c5e,
- /* 000001b0 */ 0x60626466,
- /* 000001b4 */ 0x686a6c6e,
- /* 000001b8 */ 0x70727476,
- /* NOTE: Further 17 registers set to 0. */
- },
- /*
- * NOTE: Following registers all set to 0:
- * - dmv_qpel_penalty,
- * - vp8_ctrl1,
- * - bit_cost_golden,
- * - loop_flt_delta.
- */
};
-const struct rk3288_vp8e_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
+const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
{
return &dummy_encode_reg_params;
}
* DMA coherent helpers.
*/
-int rk3288_vpu_aux_buf_alloc(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_aux_buf *buf, size_t size)
+int rockchip_vpu_aux_buf_alloc(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_aux_buf *buf, size_t size)
{
buf->cpu = dma_alloc_coherent(vpu->dev, size, &buf->dma, GFP_KERNEL);
if (!buf->cpu)
return 0;
}
-void rk3288_vpu_aux_buf_free(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_aux_buf *buf)
+void rockchip_vpu_aux_buf_free(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_aux_buf *buf)
{
dma_free_coherent(vpu->dev, buf->size, buf->cpu, buf->dma);
* Context scheduling.
*/
-static void rk3288_vpu_prepare_run(struct rk3288_vpu_ctx *ctx)
+static void rockchip_vpu_prepare_run(struct rockchip_vpu_ctx *ctx)
{
if (ctx->run_ops->prepare_run)
ctx->run_ops->prepare_run(ctx);
}
-static void __rk3288_vpu_dequeue_run_locked(struct rk3288_vpu_ctx *ctx)
+static void __rockchip_vpu_dequeue_run_locked(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_buf *src, *dst;
+ struct rockchip_vpu_buf *src, *dst;
/*
* Since ctx was dequeued from ready_ctxs list, we know that it has
* at least one buffer in each queue.
*/
- src = list_first_entry(&ctx->src_queue, struct rk3288_vpu_buf, list);
- dst = list_first_entry(&ctx->dst_queue, struct rk3288_vpu_buf, list);
+ src = list_first_entry(&ctx->src_queue, struct rockchip_vpu_buf, list);
+ dst = list_first_entry(&ctx->dst_queue, struct rockchip_vpu_buf, list);
list_del(&src->list);
list_del(&dst->list);
ctx->run.dst = dst;
}
-static struct rk3288_vpu_ctx *
-rk3288_vpu_encode_after_decode_war(struct rk3288_vpu_ctx *ctx)
+static struct rockchip_vpu_ctx *
+rockchip_vpu_encode_after_decode_war(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_dev *dev = ctx->dev;
- if (dev->was_decoding && rk3288_vpu_ctx_is_encoder(ctx))
+ if (dev->was_decoding && rockchip_vpu_ctx_is_encoder(ctx))
return dev->dummy_encode_ctx;
return ctx;
}
-static void rk3288_vpu_try_run(struct rk3288_vpu_dev *dev)
+static void rockchip_vpu_try_run(struct rockchip_vpu_dev *dev)
{
- struct rk3288_vpu_ctx *ctx = NULL;
+ struct rockchip_vpu_ctx *ctx = NULL;
unsigned long flags;
vpu_debug_enter();
if (test_and_set_bit(VPU_RUNNING, &dev->state))
/*
* The hardware is already running. We will pick another
- * run after we get the notification in rk3288_vpu_run_done().
+ * run after we get the notification in rockchip_vpu_run_done().
*/
goto out;
- ctx = list_entry(dev->ready_ctxs.next, struct rk3288_vpu_ctx, list);
+ ctx = list_entry(dev->ready_ctxs.next, struct rockchip_vpu_ctx, list);
/*
* WAR for corrupted hardware state when encoding directly after
* encoding then we need to execute a dummy encode with proper
* settings to reinitialize certain internal hardware state.
*/
- ctx = rk3288_vpu_encode_after_decode_war(ctx);
+ ctx = rockchip_vpu_encode_after_decode_war(ctx);
- if (!rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (!rockchip_vpu_ctx_is_dummy_encode(ctx)) {
list_del_init(&ctx->list);
- __rk3288_vpu_dequeue_run_locked(ctx);
+ __rockchip_vpu_dequeue_run_locked(ctx);
}
dev->current_ctx = ctx;
- dev->was_decoding = !rk3288_vpu_ctx_is_encoder(ctx);
+ dev->was_decoding = !rockchip_vpu_ctx_is_encoder(ctx);
out:
spin_unlock_irqrestore(&dev->irqlock, flags);
if (ctx) {
- rk3288_vpu_prepare_run(ctx);
- rk3288_vpu_run(ctx);
+ rockchip_vpu_prepare_run(ctx);
+ rockchip_vpu_run(ctx);
}
vpu_debug_leave();
}
-static void __rk3288_vpu_try_context_locked(struct rk3288_vpu_dev *dev,
- struct rk3288_vpu_ctx *ctx)
+static void __rockchip_vpu_try_context_locked(struct rockchip_vpu_dev *dev,
+ struct rockchip_vpu_ctx *ctx)
{
if (!list_empty(&ctx->list))
/* Context already queued. */
list_add_tail(&ctx->list, &dev->ready_ctxs);
}
-void rk3288_vpu_run_done(struct rk3288_vpu_ctx *ctx,
+void rockchip_vpu_run_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result)
{
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_dev *dev = ctx->dev;
unsigned long flags;
vpu_debug_enter();
if (ctx->run_ops->run_done)
ctx->run_ops->run_done(ctx, result);
- if (!rk3288_vpu_ctx_is_dummy_encode(ctx)) {
+ if (!rockchip_vpu_ctx_is_dummy_encode(ctx)) {
struct vb2_v4l2_buffer *src =
to_vb2_v4l2_buffer(&ctx->run.src->vb.vb2_buf);
struct vb2_v4l2_buffer *dst =
spin_lock_irqsave(&dev->irqlock, flags);
- __rk3288_vpu_try_context_locked(dev, ctx);
+ __rockchip_vpu_try_context_locked(dev, ctx);
clear_bit(VPU_RUNNING, &dev->state);
spin_unlock_irqrestore(&dev->irqlock, flags);
/* Try scheduling another run to see if we have anything left to do. */
- rk3288_vpu_try_run(dev);
+ rockchip_vpu_try_run(dev);
vpu_debug_leave();
}
-void rk3288_vpu_try_context(struct rk3288_vpu_dev *dev,
- struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_try_context(struct rockchip_vpu_dev *dev,
+ struct rockchip_vpu_ctx *ctx)
{
unsigned long flags;
spin_lock_irqsave(&dev->irqlock, flags);
- __rk3288_vpu_try_context_locked(dev, ctx);
+ __rockchip_vpu_try_context_locked(dev, ctx);
spin_unlock_irqrestore(&dev->irqlock, flags);
- rk3288_vpu_try_run(dev);
+ rockchip_vpu_try_run(dev);
vpu_debug_enter();
}
#define IS_VPU_PRIV(x) ((V4L2_CTRL_ID2CLASS(x) == V4L2_CTRL_CLASS_MPEG) && \
V4L2_CTRL_DRIVER_PRIV(x))
-int rk3288_vpu_ctrls_setup(struct rk3288_vpu_ctx *ctx,
+int rockchip_vpu_ctrls_setup(struct rockchip_vpu_ctx *ctx,
const struct v4l2_ctrl_ops *ctrl_ops,
- struct rk3288_vpu_control *controls,
+ struct rockchip_vpu_control *controls,
unsigned num_ctrls,
const char *const *(*get_menu)(u32))
{
return 0;
}
-void rk3288_vpu_ctrls_delete(struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_ctrls_delete(struct rockchip_vpu_ctx *ctx)
{
int i;
* V4L2 file operations.
*/
-static int rk3288_vpu_open(struct file *filp)
+static int rockchip_vpu_open(struct file *filp)
{
struct video_device *vdev = video_devdata(filp);
- struct rk3288_vpu_dev *dev = video_drvdata(filp);
- struct rk3288_vpu_ctx *ctx = NULL;
+ struct rockchip_vpu_dev *dev = video_drvdata(filp);
+ struct rockchip_vpu_ctx *ctx = NULL;
struct vb2_queue *q;
int ret = 0;
if (vdev == dev->vfd_enc) {
/* only for encoder */
- ret = rk3288_vpu_enc_init(ctx);
+ ret = rockchip_vpu_enc_init(ctx);
if (ret) {
vpu_err("Failed to initialize encoder context\n");
goto err_fh_free;
}
} else if (vdev == dev->vfd_dec) {
/* only for decoder */
- ret = rk3288_vpu_dec_init(ctx);
+ ret = rockchip_vpu_dec_init(ctx);
if (ret) {
vpu_err("Failed to initialize decoder context\n");
goto err_fh_free;
q->drv_priv = &ctx->fh;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->lock = &dev->vpu_mutex;
- q->buf_struct_size = sizeof(struct rk3288_vpu_buf);
+ q->buf_struct_size = sizeof(struct rockchip_vpu_buf);
if (vdev == dev->vfd_enc) {
q->ops = get_enc_queue_ops();
q->drv_priv = &ctx->fh;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->lock = &dev->vpu_mutex;
- q->buf_struct_size = sizeof(struct rk3288_vpu_buf);
+ q->buf_struct_size = sizeof(struct rockchip_vpu_buf);
if (vdev == dev->vfd_enc)
q->ops = get_enc_queue_ops();
vb2_queue_release(&ctx->vq_dst);
err_enc_dec_exit:
if (vdev == dev->vfd_enc)
- rk3288_vpu_enc_exit(ctx);
+ rockchip_vpu_enc_exit(ctx);
else if (vdev == dev->vfd_dec)
- rk3288_vpu_dec_exit(ctx);
+ rockchip_vpu_dec_exit(ctx);
err_fh_free:
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
return ret;
}
-static int rk3288_vpu_release(struct file *filp)
+static int rockchip_vpu_release(struct file *filp)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
struct video_device *vdev = video_devdata(filp);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_dev *dev = ctx->dev;
/*
* No need for extra locking because this was the last reference
v4l2_fh_exit(&ctx->fh);
if (vdev == dev->vfd_enc)
- rk3288_vpu_enc_exit(ctx);
+ rockchip_vpu_enc_exit(ctx);
else if (vdev == dev->vfd_dec)
- rk3288_vpu_dec_exit(ctx);
+ rockchip_vpu_dec_exit(ctx);
kfree(ctx);
return 0;
}
-static unsigned int rk3288_vpu_poll(struct file *filp,
+static unsigned int rockchip_vpu_poll(struct file *filp,
struct poll_table_struct *wait)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
struct vb2_queue *src_q, *dst_q;
struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
unsigned int rc = 0;
return rc;
}
-static int rk3288_vpu_mmap(struct file *filp, struct vm_area_struct *vma)
+static int rockchip_vpu_mmap(struct file *filp, struct vm_area_struct *vma)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(filp->private_data);
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
int ret;
return ret;
}
-static const struct v4l2_file_operations rk3288_vpu_fops = {
+static const struct v4l2_file_operations rockchip_vpu_fops = {
.owner = THIS_MODULE,
- .open = rk3288_vpu_open,
- .release = rk3288_vpu_release,
- .poll = rk3288_vpu_poll,
+ .open = rockchip_vpu_open,
+ .release = rockchip_vpu_release,
+ .poll = rockchip_vpu_poll,
.unlocked_ioctl = video_ioctl2,
- .mmap = rk3288_vpu_mmap,
+ .mmap = rockchip_vpu_mmap,
};
/*
* Platform driver.
*/
-static int rk3288_vpu_probe(struct platform_device *pdev)
+static int rockchip_vpu_probe(struct platform_device *pdev)
{
- struct rk3288_vpu_dev *vpu = NULL;
+ struct rockchip_vpu_dev *vpu = NULL;
DEFINE_DMA_ATTRS(attrs_novm);
DEFINE_DMA_ATTRS(attrs_nohugepage);
struct video_device *vfd;
INIT_LIST_HEAD(&vpu->ready_ctxs);
init_waitqueue_head(&vpu->run_wq);
- ret = rk3288_vpu_hw_probe(vpu);
+ ret = rockchip_vpu_hw_probe(vpu);
if (ret) {
dev_err(&pdev->dev, "vcodec_hw_probe failed\n");
goto err_hw_probe;
platform_set_drvdata(pdev, vpu);
- ret = rk3288_vpu_enc_init_dummy_ctx(vpu);
+ ret = rockchip_vpu_enc_init_dummy_ctx(vpu);
if (ret) {
dev_err(&pdev->dev, "Failed to create dummy encode context\n");
goto err_dummy_enc;
goto err_enc_alloc;
}
- vfd->fops = &rk3288_vpu_fops;
+ vfd->fops = &rockchip_vpu_fops;
vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
vfd->release = video_device_release;
vfd->lock = &vpu->vpu_mutex;
vfd->v4l2_dev = &vpu->v4l2_dev;
vfd->vfl_dir = VFL_DIR_M2M;
- snprintf(vfd->name, sizeof(vfd->name), "%s", RK3288_VPU_ENC_NAME);
+ snprintf(vfd->name, sizeof(vfd->name), "%s", ROCKCHIP_VPU_ENC_NAME);
vpu->vfd_enc = vfd;
video_set_drvdata(vfd, vpu);
}
v4l2_info(&vpu->v4l2_dev,
- "Rockchip RK3288 VPU encoder registered as /vpu/video%d\n",
+ "Rockchip VPU encoder registered as /vpu/video%d\n",
vfd->num);
/* decoder */
goto err_dec_alloc;
}
- vfd->fops = &rk3288_vpu_fops;
+ vfd->fops = &rockchip_vpu_fops;
vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
vfd->release = video_device_release;
vfd->lock = &vpu->vpu_mutex;
vfd->v4l2_dev = &vpu->v4l2_dev;
vfd->vfl_dir = VFL_DIR_M2M;
- snprintf(vfd->name, sizeof(vfd->name), "%s", RK3288_VPU_DEC_NAME);
+ snprintf(vfd->name, sizeof(vfd->name), "%s", ROCKCHIP_VPU_DEC_NAME);
vpu->vfd_dec = vfd;
video_set_drvdata(vfd, vpu);
}
v4l2_info(&vpu->v4l2_dev,
- "Rockchip RK3288 VPU decoder registered as /vpu/video%d\n",
+ "Rockchip VPU decoder registered as /vpu/video%d\n",
vfd->num);
vpu_debug_leave();
err_enc_reg:
video_device_release(vpu->vfd_enc);
err_enc_alloc:
- rk3288_vpu_enc_free_dummy_ctx(vpu);
+ rockchip_vpu_enc_free_dummy_ctx(vpu);
err_dummy_enc:
v4l2_device_unregister(&vpu->v4l2_dev);
err_v4l2_dev_reg:
err_dma_contig_vm:
vb2_dma_contig_cleanup_ctx(vpu->alloc_ctx);
err_dma_contig:
- rk3288_vpu_hw_remove(vpu);
+ rockchip_vpu_hw_remove(vpu);
err_hw_probe:
pr_debug("%s-- with error\n", __func__);
vpu_debug_leave();
return ret;
}
-static int rk3288_vpu_remove(struct platform_device *pdev)
+static int rockchip_vpu_remove(struct platform_device *pdev)
{
- struct rk3288_vpu_dev *vpu = platform_get_drvdata(pdev);
+ struct rockchip_vpu_dev *vpu = platform_get_drvdata(pdev);
vpu_debug_enter();
video_unregister_device(vpu->vfd_dec);
video_unregister_device(vpu->vfd_enc);
- rk3288_vpu_enc_free_dummy_ctx(vpu);
+ rockchip_vpu_enc_free_dummy_ctx(vpu);
v4l2_device_unregister(&vpu->v4l2_dev);
vb2_dma_contig_cleanup_ctx(vpu->alloc_ctx_vm);
vb2_dma_contig_cleanup_ctx(vpu->alloc_ctx);
- rk3288_vpu_hw_remove(vpu);
+ rockchip_vpu_hw_remove(vpu);
vpu_debug_leave();
MODULE_DEVICE_TABLE(platform, vpu_driver_ids);
#ifdef CONFIG_OF
-static const struct of_device_id of_rk3288_vpu_match[] = {
+static const struct of_device_id of_rockchip_vpu_match[] = {
{ .compatible = "rockchip,rk3288-vpu", },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, of_rk3288_vpu_match);
+MODULE_DEVICE_TABLE(of, of_rockchip_vpu_match);
#endif
#ifdef CONFIG_PM_SLEEP
-static int rk3288_vpu_suspend(struct device *dev)
+static int rockchip_vpu_suspend(struct device *dev)
{
- struct rk3288_vpu_dev *vpu = dev_get_drvdata(dev);
+ struct rockchip_vpu_dev *vpu = dev_get_drvdata(dev);
set_bit(VPU_SUSPENDED, &vpu->state);
wait_event(vpu->run_wq, vpu->current_ctx == NULL);
return 0;
}
-static int rk3288_vpu_resume(struct device *dev)
+static int rockchip_vpu_resume(struct device *dev)
{
- struct rk3288_vpu_dev *vpu = dev_get_drvdata(dev);
+ struct rockchip_vpu_dev *vpu = dev_get_drvdata(dev);
clear_bit(VPU_SUSPENDED, &vpu->state);
- rk3288_vpu_try_run(vpu);
+ rockchip_vpu_try_run(vpu);
return 0;
}
#endif
-static const struct dev_pm_ops rk3288_vpu_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(rk3288_vpu_suspend, rk3288_vpu_resume)
+static const struct dev_pm_ops rockchip_vpu_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(rockchip_vpu_suspend, rockchip_vpu_resume)
};
-static struct platform_driver rk3288_vpu_driver = {
- .probe = rk3288_vpu_probe,
- .remove = rk3288_vpu_remove,
+static struct platform_driver rockchip_vpu_driver = {
+ .probe = rockchip_vpu_probe,
+ .remove = rockchip_vpu_remove,
.id_table = vpu_driver_ids,
.driver = {
- .name = RK3288_VPU_NAME,
+ .name = ROCKCHIP_VPU_NAME,
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(of_rk3288_vpu_match),
- .pm = &rk3288_vpu_pm_ops,
+ .of_match_table = of_match_ptr(of_rockchip_vpu_match),
+ .pm = &rockchip_vpu_pm_ops,
},
};
-module_platform_driver(rk3288_vpu_driver);
+module_platform_driver(rockchip_vpu_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
#include "rockchip_vpu_hw.h"
-#define RK3288_VPU_NAME "rk3288-vpu"
-#define RK3288_VPU_DEC_NAME "rk3288-vpu-dec"
-#define RK3288_VPU_ENC_NAME "rk3288-vpu-enc"
+#define ROCKCHIP_VPU_NAME "rockchip-vpu"
+#define ROCKCHIP_VPU_DEC_NAME "rockchip-vpu-dec"
+#define ROCKCHIP_VPU_ENC_NAME "rockchip-vpu-enc"
#define V4L2_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0x1000)
#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
-#define RK3288_VPU_MAX_CTRLS 32
+#define ROCKCHIP_VPU_MAX_CTRLS 32
#define MB_DIM 16
#define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, MB_DIM)
#define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, MB_DIM)
-struct rk3288_vpu_variant;
-struct rk3288_vpu_ctx;
-struct rk3288_vpu_codec_ops;
+struct rockchip_vpu_variant;
+struct rockchip_vpu_ctx;
+struct rockchip_vpu_codec_ops;
/**
- * enum rk3288_vpu_codec_mode - codec operating mode.
+ * enum rockchip_vpu_codec_mode - codec operating mode.
* @RK_VPU_CODEC_NONE: No operating mode. Used for RAW video formats.
- * @RK_VPU_CODEC_H264D: H264 decoder.
- * @RK_VPU_CODEC_VP8D: VP8 decoder.
- * @RK_VPU_CODEC_H264E: H264 encoder.
- * @RK_VPU_CODEC_VP8E: VP8 encoder.
+ * @RK3288_VPU_CODEC_H264D: Rk3288 H264 decoder.
+ * @RK3288_VPU_CODEC_VP8D: Rk3288 VP8 decoder.
+ * @RK3288_VPU_CODEC_VP8E: Rk3288 VP8 encoder.
*/
-enum rk3288_vpu_codec_mode {
+enum rockchip_vpu_codec_mode {
RK_VPU_CODEC_NONE = -1,
- RK_VPU_CODEC_H264D,
- RK_VPU_CODEC_VP8D,
- RK_VPU_CODEC_H264E,
- RK_VPU_CODEC_VP8E
+ RK3288_VPU_CODEC_H264D,
+ RK3288_VPU_CODEC_VP8D,
+ RK3288_VPU_CODEC_VP8E
};
/**
- * enum rk3288_vpu_plane - indices of planes inside a VB2 buffer.
+ * enum rockchip_vpu_plane - indices of planes inside a VB2 buffer.
* @PLANE_Y: Plane containing luminance data (also denoted as Y).
* @PLANE_CB_CR: Plane containing interleaved chrominance data (also
* denoted as CbCr).
* @PLANE_CB: Plane containing CB part of chrominance data.
* @PLANE_CR: Plane containing CR part of chrominance data.
*/
-enum rk3288_vpu_plane {
+enum rockchip_vpu_plane {
PLANE_Y = 0,
PLANE_CB_CR = 1,
PLANE_CB = 1,
};
/**
- * struct rk3288_vpu_vp8e_buf_data - mode-specific per-buffer data
+ * struct rockchip_vpu_vp8e_buf_data - mode-specific per-buffer data
* @dct_offset: Offset inside the buffer to DCT partition.
* @hdr_size: Size of header data in the buffer.
* @ext_hdr_size: Size of ext header data in the buffer.
* @dct_size: Size of DCT partition in the buffer.
* @header: Frame header to copy to destination buffer.
*/
-struct rk3288_vpu_vp8e_buf_data {
+struct rockchip_vpu_vp8e_buf_data {
size_t dct_offset;
size_t hdr_size;
size_t ext_hdr_size;
size_t dct_size;
- u8 header[RK3288_HEADER_SIZE];
+ u8 header[ROCKCHIP_HEADER_SIZE];
};
/**
- * struct rk3288_vpu_buf - Private data related to each VB2 buffer.
+ * struct rockchip_vpu_buf - Private data related to each VB2 buffer.
* @vb: Pointer to related VB2 buffer.
* @list: List head for queuing in buffer queue.
- * @flags: Buffer state. See enum rk3288_vpu_buf_flags.
*/
-struct rk3288_vpu_buf {
+struct rockchip_vpu_buf {
struct vb2_v4l2_buffer vb;
struct list_head list;
/* Mode-specific data. */
union {
- struct rk3288_vpu_vp8e_buf_data vp8e;
+ struct rockchip_vpu_vp8e_buf_data vp8e;
};
};
/**
- * enum rk3288_vpu_state - bitwise flags indicating hardware state.
+ * enum rockchip_vpu_state - bitwise flags indicating hardware state.
* @VPU_RUNNING: The hardware has been programmed for operation
* and is running at the moment.
* @VPU_SUSPENDED: System is entering sleep state and no more runs
* should be executed on hardware.
*/
-enum rk3288_vpu_state {
+enum rockchip_vpu_state {
VPU_RUNNING = BIT(0),
VPU_SUSPENDED = BIT(1),
};
/**
- * struct rk3288_vpu_dev - driver data
+ * struct rockchip_vpu_dev - driver data
* @v4l2_dev: V4L2 device to register video devices for.
* @vfd_dec: Video device for decoder.
* @vfd_enc: Video device for encoder.
* @dummy_encode_dst: Desintation buffer used for dummy frame encoding.
* @was_decoding: Indicates whether last run context was a decoder.
*/
-struct rk3288_vpu_dev {
+struct rockchip_vpu_dev {
struct v4l2_device v4l2_dev;
struct video_device *vfd_dec;
struct video_device *vfd_enc;
spinlock_t irqlock;
unsigned long state;
struct list_head ready_ctxs;
- const struct rk3288_vpu_variant *variant;
- struct rk3288_vpu_ctx *current_ctx;
+ const struct rockchip_vpu_variant *variant;
+ struct rockchip_vpu_ctx *current_ctx;
wait_queue_head_t run_wq;
struct delayed_work watchdog_work;
- struct rk3288_vpu_ctx *dummy_encode_ctx;
- struct rk3288_vpu_aux_buf dummy_encode_src[VIDEO_MAX_PLANES];
- struct rk3288_vpu_aux_buf dummy_encode_dst;
+ struct rockchip_vpu_ctx *dummy_encode_ctx;
+ struct rockchip_vpu_aux_buf dummy_encode_src[VIDEO_MAX_PLANES];
+ struct rockchip_vpu_aux_buf dummy_encode_dst;
bool was_decoding;
};
/**
- * struct rk3288_vpu_run_ops - per context operations on run data.
+ * struct rockchip_vpu_run_ops - per context operations on run data.
* @prepare_run: Called when the context was selected for running
* to prepare operating mode specific data.
* @run_done: Called when hardware completed the run to collect
* operating mode specific data from hardware and
* finalize the processing.
*/
-struct rk3288_vpu_run_ops {
- void (*prepare_run)(struct rk3288_vpu_ctx *);
- void (*run_done)(struct rk3288_vpu_ctx *, enum vb2_buffer_state);
+struct rockchip_vpu_run_ops {
+ void (*prepare_run)(struct rockchip_vpu_ctx *);
+ void (*run_done)(struct rockchip_vpu_ctx *, enum vb2_buffer_state);
};
/**
- * struct rk3288_vpu_vp8e_run - per-run data specific to VP8 encoding.
+ * struct rockchip_vpu_vp8e_run - per-run data specific to VP8 encoding.
* @reg_params: Pointer to a buffer containing register values prepared
* by user space.
*/
-struct rk3288_vpu_vp8e_run {
- const struct rk3288_vp8e_reg_params *reg_params;
+struct rockchip_vpu_vp8e_run {
+ const struct rockchip_reg_params *reg_params;
};
/**
- * struct rk3288_vpu_vp8d_run - per-run data specific to VP8 decoding.
+ * struct rockchip_vpu_vp8d_run - per-run data specific to VP8 decoding.
* @frame_hdr: Pointer to a buffer containing per-run frame data which
* is needed by setting vpu register.
*/
-struct rk3288_vpu_vp8d_run {
+struct rockchip_vpu_vp8d_run {
const struct v4l2_ctrl_vp8_frame_hdr *frame_hdr;
};
/**
- * struct rk3288_vpu_h264d_run - per-run data specific to H264 decoding.
+ * struct rockchip_vpu_h264d_run - per-run data specific to H264 decoding.
* @sps: Pointer to a buffer containing H264 SPS.
* @pps: Pointer to a buffer containing H264 PPS.
* @scaling_matrix: Pointer to a buffer containing scaling matrix.
* @dpb_map: Map of indices used in ref_pic_list_* into indices to
* reordered DPB array.
*/
-struct rk3288_vpu_h264d_run {
+struct rockchip_vpu_h264d_run {
const struct v4l2_ctrl_h264_sps *sps;
const struct v4l2_ctrl_h264_pps *pps;
const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;
};
/**
- * struct rk3288_vpu_run - per-run data for hardware code.
+ * struct rockchip_vpu_run - per-run data for hardware code.
* @src: Source buffer to be processed.
* @dst: Destination buffer to be processed.
* @priv_src: Hardware private source buffer.
* @priv_dst: Hardware private destination buffer.
*/
-struct rk3288_vpu_run {
+struct rockchip_vpu_run {
/* Generic for more than one operating mode. */
- struct rk3288_vpu_buf *src;
- struct rk3288_vpu_buf *dst;
+ struct rockchip_vpu_buf *src;
+ struct rockchip_vpu_buf *dst;
- struct rk3288_vpu_aux_buf priv_src;
- struct rk3288_vpu_aux_buf priv_dst;
+ struct rockchip_vpu_aux_buf priv_src;
+ struct rockchip_vpu_aux_buf priv_dst;
/* Specific for particular operating modes. */
union {
- struct rk3288_vpu_vp8e_run vp8e;
- struct rk3288_vpu_vp8d_run vp8d;
- struct rk3288_vpu_h264d_run h264d;
+ struct rockchip_vpu_vp8e_run vp8e;
+ struct rockchip_vpu_vp8d_run vp8d;
+ struct rockchip_vpu_h264d_run h264d;
/* Other modes will need different data. */
};
};
/**
- * struct rk3288_vpu_ctx - Context (instance) private data.
+ * struct rockchip_vpu_ctx - Context (instance) private data.
*
* @dev: VPU driver data to which the context belongs.
* @fh: V4L2 file handler.
* @run_ops: Set of operations related to currently scheduled run.
* @hw: Structure containing hardware-related context.
*/
-struct rk3288_vpu_ctx {
- struct rk3288_vpu_dev *dev;
+struct rockchip_vpu_ctx {
+ struct rockchip_vpu_dev *dev;
struct v4l2_fh fh;
/* Format info */
- struct rk3288_vpu_fmt *vpu_src_fmt;
+ struct rockchip_vpu_fmt *vpu_src_fmt;
struct v4l2_pix_format_mplane src_fmt;
- struct rk3288_vpu_fmt *vpu_dst_fmt;
+ struct rockchip_vpu_fmt *vpu_dst_fmt;
struct v4l2_pix_format_mplane dst_fmt;
/* VB2 queue data */
struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME];
/* Controls */
- struct v4l2_ctrl *ctrls[RK3288_VPU_MAX_CTRLS];
+ struct v4l2_ctrl *ctrls[ROCKCHIP_VPU_MAX_CTRLS];
struct v4l2_ctrl_handler ctrl_handler;
unsigned num_ctrls;
/* Various runtime data */
struct list_head list;
- struct rk3288_vpu_run run;
- const struct rk3288_vpu_run_ops *run_ops;
- struct rk3288_vpu_hw_ctx hw;
+ struct rockchip_vpu_run run;
+ const struct rockchip_vpu_run_ops *run_ops;
+ struct rockchip_vpu_hw_ctx hw;
};
/**
- * struct rk3288_vpu_fmt - information about supported video formats.
+ * struct rockchip_vpu_fmt - information about supported video formats.
* @name: Human readable name of the format.
* @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
* @codec_mode: Codec mode related to this format. See
- * enum rk3288_vpu_codec_mode.
+ * enum rockchip_vpu_codec_mode.
* @num_planes: Number of planes used by this format.
* @depth: Depth of each plane in bits per pixel.
* @enc_fmt: Format identifier for encoder registers.
*/
-struct rk3288_vpu_fmt {
+struct rockchip_vpu_fmt {
char *name;
u32 fourcc;
- enum rk3288_vpu_codec_mode codec_mode;
+ enum rockchip_vpu_codec_mode codec_mode;
int num_planes;
u8 depth[VIDEO_MAX_PLANES];
- enum rk3288_vpu_enc_fmt enc_fmt;
+ enum rockchip_vpu_enc_fmt enc_fmt;
};
/**
- * struct rk3288_vpu_control - information about controls to be registered.
+ * struct rockchip_vpu_control - information about controls to be registered.
* @id: Control ID.
* @type: Type of the control.
* @name: Human readable name of the control.
*
* See also struct v4l2_ctrl_config.
*/
-struct rk3288_vpu_control {
+struct rockchip_vpu_control {
u32 id;
enum v4l2_ctrl_type type;
}
/* Structure access helpers. */
-static inline struct rk3288_vpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
+static inline struct rockchip_vpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
{
- return container_of(fh, struct rk3288_vpu_ctx, fh);
+ return container_of(fh, struct rockchip_vpu_ctx, fh);
}
-static inline struct rk3288_vpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
+static inline struct rockchip_vpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
{
- return container_of(ctrl->handler, struct rk3288_vpu_ctx, ctrl_handler);
+ return container_of(ctrl->handler,
+ struct rockchip_vpu_ctx, ctrl_handler);
}
-static inline struct rk3288_vpu_buf *vb_to_buf(struct vb2_buffer *vb)
+static inline struct rockchip_vpu_buf *vb_to_buf(struct vb2_buffer *vb)
{
- return container_of(to_vb2_v4l2_buffer(vb), struct rk3288_vpu_buf, vb);
+ return container_of(to_vb2_v4l2_buffer(vb),
+ struct rockchip_vpu_buf, vb);
}
-static inline bool rk3288_vpu_ctx_is_encoder(struct rk3288_vpu_ctx *ctx)
+static inline bool rockchip_vpu_ctx_is_encoder(struct rockchip_vpu_ctx *ctx)
{
return ctx->vpu_dst_fmt->codec_mode != RK_VPU_CODEC_NONE;
}
-static inline bool rk3288_vpu_ctx_is_dummy_encode(struct rk3288_vpu_ctx *ctx)
+static inline bool
+rockchip_vpu_ctx_is_dummy_encode(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_dev *dev = ctx->dev;
return ctx == dev->dummy_encode_ctx;
}
-int rk3288_vpu_ctrls_setup(struct rk3288_vpu_ctx *ctx,
+int rockchip_vpu_ctrls_setup(struct rockchip_vpu_ctx *ctx,
const struct v4l2_ctrl_ops *ctrl_ops,
- struct rk3288_vpu_control *controls,
+ struct rockchip_vpu_control *controls,
unsigned num_ctrls,
const char *const *(*get_menu)(u32));
-void rk3288_vpu_ctrls_delete(struct rk3288_vpu_ctx *ctx);
+void rockchip_vpu_ctrls_delete(struct rockchip_vpu_ctx *ctx);
-void rk3288_vpu_try_context(struct rk3288_vpu_dev *dev,
- struct rk3288_vpu_ctx *ctx);
+void rockchip_vpu_try_context(struct rockchip_vpu_dev *dev,
+ struct rockchip_vpu_ctx *ctx);
-void rk3288_vpu_run_done(struct rk3288_vpu_ctx *ctx,
+void rockchip_vpu_run_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result);
-int rk3288_vpu_aux_buf_alloc(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_aux_buf *buf, size_t size);
-void rk3288_vpu_aux_buf_free(struct rk3288_vpu_dev *vpu,
- struct rk3288_vpu_aux_buf *buf);
+int rockchip_vpu_aux_buf_alloc(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_aux_buf *buf, size_t size);
+void rockchip_vpu_aux_buf_free(struct rockchip_vpu_dev *vpu,
+ struct rockchip_vpu_aux_buf *buf);
/* Register accessors. */
-static inline void vepu_write_relaxed(struct rk3288_vpu_dev *vpu,
+static inline void vepu_write_relaxed(struct rockchip_vpu_dev *vpu,
u32 val, u32 reg)
{
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
writel_relaxed(val, vpu->enc_base + reg);
}
-static inline void vepu_write(struct rk3288_vpu_dev *vpu, u32 val, u32 reg)
+static inline void vepu_write(struct rockchip_vpu_dev *vpu, u32 val, u32 reg)
{
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
writel(val, vpu->enc_base + reg);
}
-static inline u32 vepu_read(struct rk3288_vpu_dev *vpu, u32 reg)
+static inline u32 vepu_read(struct rockchip_vpu_dev *vpu, u32 reg)
{
u32 val = readl(vpu->enc_base + reg);
return val;
}
-static inline void vdpu_write_relaxed(struct rk3288_vpu_dev *vpu,
+static inline void vdpu_write_relaxed(struct rockchip_vpu_dev *vpu,
u32 val, u32 reg)
{
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
writel_relaxed(val, vpu->dec_base + reg);
}
-static inline void vdpu_write(struct rk3288_vpu_dev *vpu, u32 val, u32 reg)
+static inline void vdpu_write(struct rockchip_vpu_dev *vpu, u32 val, u32 reg)
{
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
writel(val, vpu->dec_base + reg);
}
-static inline u32 vdpu_read(struct rk3288_vpu_dev *vpu, u32 reg)
+static inline u32 vdpu_read(struct rockchip_vpu_dev *vpu, u32 reg)
{
u32 val = readl(vpu->dec_base + reg);
#define DEF_SRC_FMT_DEC V4L2_PIX_FMT_H264_SLICE
#define DEF_DST_FMT_DEC V4L2_PIX_FMT_NV12
-#define RK3288_DEC_MIN_WIDTH 48U
-#define RK3288_DEC_MAX_WIDTH 3840U
-#define RK3288_DEC_MIN_HEIGHT 48U
-#define RK3288_DEC_MAX_HEIGHT 2160U
+#define ROCKCHIP_DEC_MIN_WIDTH 48U
+#define ROCKCHIP_DEC_MAX_WIDTH 3840U
+#define ROCKCHIP_DEC_MIN_HEIGHT 48U
+#define ROCKCHIP_DEC_MAX_HEIGHT 2160U
-#define RK3288_H264_MAX_SLICES_PER_FRAME 16
+#define ROCKCHIP_H264_MAX_SLICES_PER_FRAME 16
-static struct rk3288_vpu_fmt formats[] = {
+static struct rockchip_vpu_fmt formats[] = {
{
.name = "4:2:0 1 plane Y/CbCr",
.fourcc = V4L2_PIX_FMT_NV12,
{
.name = "Slices of H264 Encoded Stream",
.fourcc = V4L2_PIX_FMT_H264_SLICE,
- .codec_mode = RK_VPU_CODEC_H264D,
+ .codec_mode = RK3288_VPU_CODEC_H264D,
.num_planes = 1,
},
{
.name = "Frames of VP8 Encoded Stream",
.fourcc = V4L2_PIX_FMT_VP8_FRAME,
- .codec_mode = RK_VPU_CODEC_VP8D,
+ .codec_mode = RK3288_VPU_CODEC_VP8D,
.num_planes = 1,
},
};
-static struct rk3288_vpu_fmt *find_format(u32 fourcc, bool bitstream)
+static struct rockchip_vpu_fmt *find_format(u32 fourcc, bool bitstream)
{
unsigned int i;
/* Indices of controls that need to be accessed directly. */
enum {
- RK3288_VPU_DEC_CTRL_H264_SPS,
- RK3288_VPU_DEC_CTRL_H264_PPS,
- RK3288_VPU_DEC_CTRL_H264_SCALING_MATRIX,
- RK3288_VPU_DEC_CTRL_H264_SLICE_PARAM,
- RK3288_VPU_DEC_CTRL_H264_DECODE_PARAM,
- RK3288_VPU_DEC_CTRL_VP8_FRAME_HDR,
+ ROCKCHIP_VPU_DEC_CTRL_H264_SPS,
+ ROCKCHIP_VPU_DEC_CTRL_H264_PPS,
+ ROCKCHIP_VPU_DEC_CTRL_H264_SCALING_MATRIX,
+ ROCKCHIP_VPU_DEC_CTRL_H264_SLICE_PARAM,
+ ROCKCHIP_VPU_DEC_CTRL_H264_DECODE_PARAM,
+ ROCKCHIP_VPU_DEC_CTRL_VP8_FRAME_HDR,
};
-static struct rk3288_vpu_control controls[] = {
+static struct rockchip_vpu_control controls[] = {
/* H264 slice-based interface. */
- [RK3288_VPU_DEC_CTRL_H264_SPS] = {
+ [ROCKCHIP_VPU_DEC_CTRL_H264_SPS] = {
.id = V4L2_CID_MPEG_VIDEO_H264_SPS,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "H264 SPS Parameters",
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_DEC_CTRL_H264_PPS] = {
+ [ROCKCHIP_VPU_DEC_CTRL_H264_PPS] = {
.id = V4L2_CID_MPEG_VIDEO_H264_PPS,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "H264 PPS Parameters",
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_DEC_CTRL_H264_SCALING_MATRIX] = {
+ [ROCKCHIP_VPU_DEC_CTRL_H264_SCALING_MATRIX] = {
.id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "H264 Scaling Matrix",
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_DEC_CTRL_H264_SLICE_PARAM] = {
+ [ROCKCHIP_VPU_DEC_CTRL_H264_SLICE_PARAM] = {
.id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAM,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "H264 Slice Parameters",
.max_stores = VIDEO_MAX_FRAME,
.elem_size = sizeof(struct v4l2_ctrl_h264_slice_param),
- .dims = { RK3288_H264_MAX_SLICES_PER_FRAME, },
+ .dims = { ROCKCHIP_H264_MAX_SLICES_PER_FRAME, },
.can_store = true,
},
- [RK3288_VPU_DEC_CTRL_H264_DECODE_PARAM] = {
+ [ROCKCHIP_VPU_DEC_CTRL_H264_DECODE_PARAM] = {
.id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAM,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "H264 Decode Parameters",
.elem_size = sizeof(struct v4l2_ctrl_h264_decode_param),
.can_store = true,
},
- [RK3288_VPU_DEC_CTRL_VP8_FRAME_HDR] = {
+ [ROCKCHIP_VPU_DEC_CTRL_VP8_FRAME_HDR] = {
.id = V4L2_CID_MPEG_VIDEO_VP8_FRAME_HDR,
.type = V4L2_CTRL_TYPE_PRIVATE,
.name = "VP8 Frame Header Parameters",
},
};
-static inline const void *get_ctrl_ptr(struct rk3288_vpu_ctx *ctx, unsigned id)
+static inline const void *get_ctrl_ptr(struct rockchip_vpu_ctx *ctx, unsigned id)
{
struct v4l2_ctrl *ctrl = ctx->ctrls[id];
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
- struct rk3288_vpu_dev *dev = video_drvdata(file);
+ struct rockchip_vpu_dev *dev = video_drvdata(file);
vpu_debug_enter();
- strlcpy(cap->driver, RK3288_VPU_DEC_NAME, sizeof(cap->driver));
+ strlcpy(cap->driver, ROCKCHIP_VPU_DEC_NAME, sizeof(cap->driver));
strlcpy(cap->card, dev->pdev->name, sizeof(cap->card));
- strlcpy(cap->bus_info, "platform:" RK3288_VPU_NAME,
+ strlcpy(cap->bus_info, "platform:" ROCKCHIP_VPU_NAME,
sizeof(cap->bus_info));
/*
struct v4l2_frmsizeenum *fsize)
{
struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
if (fsize->index != 0) {
vpu_debug(0, "invalid frame size index (expected 0, got %d)\n",
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
- s->min_width = RK3288_DEC_MIN_WIDTH;
- s->max_width = RK3288_DEC_MAX_WIDTH;
+ s->min_width = ROCKCHIP_DEC_MIN_WIDTH;
+ s->max_width = ROCKCHIP_DEC_MAX_WIDTH;
s->step_width = MB_DIM;
- s->min_height = RK3288_DEC_MIN_HEIGHT;
- s->max_height = RK3288_DEC_MAX_HEIGHT;
+ s->min_height = ROCKCHIP_DEC_MIN_HEIGHT;
+ s->max_height = ROCKCHIP_DEC_MAX_HEIGHT;
s->step_height = MB_DIM;
return 0;
static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool out)
{
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
int i, j = 0;
vpu_debug_enter();
static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
vpu_debug_enter();
static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
char str[5];
/* Limit to hardware min/max. */
pix_fmt_mp->width = clamp(pix_fmt_mp->width,
- RK3288_DEC_MIN_WIDTH, RK3288_DEC_MAX_WIDTH);
+ ROCKCHIP_DEC_MIN_WIDTH, ROCKCHIP_DEC_MAX_WIDTH);
pix_fmt_mp->height = clamp(pix_fmt_mp->height,
- RK3288_DEC_MIN_HEIGHT, RK3288_DEC_MAX_HEIGHT);
+ ROCKCHIP_DEC_MIN_HEIGHT, ROCKCHIP_DEC_MAX_HEIGHT);
/* Round up to macroblocks. */
pix_fmt_mp->width = round_up(pix_fmt_mp->width, MB_DIM);
static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
unsigned int mb_width, mb_height;
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
int ret = 0;
int i;
static int vidioc_reqbufs(struct file *file, void *priv,
struct v4l2_requestbuffers *reqbufs)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_querybuf(struct file *file, void *priv,
struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
/* Queue a buffer */
static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
int i;
/* Dequeue a buffer */
static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_expbuf(struct file *file, void *priv,
struct v4l2_exportbuffer *eb)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_streamoff(struct file *file, void *priv,
enum v4l2_buf_type type)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
return ret;
}
-static void rk3288_vpu_dec_set_dpb(struct rk3288_vpu_ctx *ctx,
+static void rockchip_vpu_dec_set_dpb(struct rockchip_vpu_ctx *ctx,
struct v4l2_ctrl *ctrl)
{
struct v4l2_ctrl_h264_decode_param *dec_param = ctrl->p_new.p;
dec_param->ref_pic_list_p0[i] = 0;
}
-static int rk3288_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl)
+static int rockchip_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl)
{
- struct rk3288_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
+ struct rockchip_vpu_dev *dev = ctx->dev;
int ret = 0;
vpu_debug_enter();
case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAM:
if (ctrl->store)
break;
- rk3288_vpu_dec_set_dpb(ctx, ctrl);
+ rockchip_vpu_dec_set_dpb(ctx, ctrl);
break;
default:
return ret;
}
-static const struct v4l2_ctrl_ops rk3288_vpu_dec_ctrl_ops = {
- .s_ctrl = rk3288_vpu_dec_s_ctrl,
+static const struct v4l2_ctrl_ops rockchip_vpu_dec_ctrl_ops = {
+ .s_ctrl = rockchip_vpu_dec_s_ctrl,
};
-static const struct v4l2_ioctl_ops rk3288_vpu_dec_ioctl_ops = {
+static const struct v4l2_ioctl_ops rockchip_vpu_dec_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_framesizes = vidioc_enum_framesizes,
.vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
.vidioc_streamoff = vidioc_streamoff,
};
-static int rk3288_vpu_queue_setup(struct vb2_queue *vq,
+static int rockchip_vpu_queue_setup(struct vb2_queue *vq,
const void *parg,
unsigned int *buf_count,
unsigned int *plane_count,
unsigned int psize[], void *allocators[])
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
int ret = 0;
vpu_debug_enter();
return ret;
}
-static int rk3288_vpu_buf_init(struct vb2_buffer *vb)
+static int rockchip_vpu_buf_init(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
vpu_debug_enter();
return 0;
}
-static void rk3288_vpu_buf_cleanup(struct vb2_buffer *vb)
+static void rockchip_vpu_buf_cleanup(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
vpu_debug_enter();
vpu_debug_leave();
}
-static int rk3288_vpu_buf_prepare(struct vb2_buffer *vb)
+static int rockchip_vpu_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
int ret = 0;
int i;
return ret;
}
-static int rk3288_vpu_start_streaming(struct vb2_queue *q, unsigned int count)
+static int rockchip_vpu_start_streaming(struct vb2_queue *q, unsigned int count)
{
int ret = 0;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
bool ready = false;
vpu_debug_enter();
if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
- ret = rk3288_vpu_init(ctx);
+ ret = rockchip_vpu_init(ctx);
if (ret < 0) {
- vpu_err("rk3288_vpu_init failed\n");
+ vpu_err("rockchip_vpu_init failed\n");
return ret;
}
}
if (ready)
- rk3288_vpu_try_context(dev, ctx);
+ rockchip_vpu_try_context(dev, ctx);
vpu_debug_leave();
return 0;
}
-static void rk3288_vpu_stop_streaming(struct vb2_queue *q)
+static void rockchip_vpu_stop_streaming(struct vb2_queue *q)
{
unsigned long flags;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
- struct rk3288_vpu_buf *b;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_buf *b;
LIST_HEAD(queue);
int i;
wait_event(dev->run_wq, dev->current_ctx != ctx);
while (!list_empty(&queue)) {
- b = list_first_entry(&queue, struct rk3288_vpu_buf, list);
+ b = list_first_entry(&queue, struct rockchip_vpu_buf, list);
for (i = 0; i < b->vb.vb2_buf.num_planes; i++)
vb2_set_plane_payload(&b->vb.vb2_buf, i, 0);
vb2_buffer_done(&b->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
- rk3288_vpu_deinit(ctx);
+ rockchip_vpu_deinit(ctx);
vpu_debug_leave();
}
-static void rk3288_vpu_buf_queue(struct vb2_buffer *vb)
+static void rockchip_vpu_buf_queue(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
- struct rk3288_vpu_buf *vpu_buf;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_buf *vpu_buf;
unsigned long flags;
vpu_debug_enter();
}
if (vb2_is_streaming(&ctx->vq_src) && vb2_is_streaming(&ctx->vq_dst))
- rk3288_vpu_try_context(dev, ctx);
+ rockchip_vpu_try_context(dev, ctx);
vpu_debug_leave();
}
-static struct vb2_ops rk3288_vpu_dec_qops = {
- .queue_setup = rk3288_vpu_queue_setup,
+static struct vb2_ops rockchip_vpu_dec_qops = {
+ .queue_setup = rockchip_vpu_queue_setup,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
- .buf_init = rk3288_vpu_buf_init,
- .buf_prepare = rk3288_vpu_buf_prepare,
- .buf_cleanup = rk3288_vpu_buf_cleanup,
- .start_streaming = rk3288_vpu_start_streaming,
- .stop_streaming = rk3288_vpu_stop_streaming,
- .buf_queue = rk3288_vpu_buf_queue,
+ .buf_init = rockchip_vpu_buf_init,
+ .buf_prepare = rockchip_vpu_buf_prepare,
+ .buf_cleanup = rockchip_vpu_buf_cleanup,
+ .start_streaming = rockchip_vpu_start_streaming,
+ .stop_streaming = rockchip_vpu_stop_streaming,
+ .buf_queue = rockchip_vpu_buf_queue,
};
struct vb2_ops *get_dec_queue_ops(void)
{
- return &rk3288_vpu_dec_qops;
+ return &rockchip_vpu_dec_qops;
}
const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void)
{
- return &rk3288_vpu_dec_ioctl_ops;
+ return &rockchip_vpu_dec_ioctl_ops;
}
-static void rk3288_vpu_dec_prepare_run(struct rk3288_vpu_ctx *ctx)
+static void rockchip_vpu_dec_prepare_run(struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *src = to_vb2_v4l2_buffer(&ctx->run.src->vb.vb2_buf);
if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) {
ctx->run.h264d.sps = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_H264_SPS);
+ ROCKCHIP_VPU_DEC_CTRL_H264_SPS);
ctx->run.h264d.pps = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_H264_PPS);
+ ROCKCHIP_VPU_DEC_CTRL_H264_PPS);
ctx->run.h264d.scaling_matrix = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_H264_SCALING_MATRIX);
+ ROCKCHIP_VPU_DEC_CTRL_H264_SCALING_MATRIX);
ctx->run.h264d.slice_param = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_H264_SLICE_PARAM);
+ ROCKCHIP_VPU_DEC_CTRL_H264_SLICE_PARAM);
ctx->run.h264d.decode_param = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_H264_DECODE_PARAM);
+ ROCKCHIP_VPU_DEC_CTRL_H264_DECODE_PARAM);
} else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP8_FRAME) {
ctx->run.vp8d.frame_hdr = get_ctrl_ptr(ctx,
- RK3288_VPU_DEC_CTRL_VP8_FRAME_HDR);
+ ROCKCHIP_VPU_DEC_CTRL_VP8_FRAME_HDR);
}
}
-static void rk3288_vpu_dec_run_done(struct rk3288_vpu_ctx *ctx,
+static void rockchip_vpu_dec_run_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result)
{
struct v4l2_plane_pix_format *plane_fmts = ctx->dst_fmt.plane_fmt;
vb2_set_plane_payload(dst, i, plane_fmts[i].sizeimage);
}
-static const struct rk3288_vpu_run_ops rk3288_vpu_dec_run_ops = {
- .prepare_run = rk3288_vpu_dec_prepare_run,
- .run_done = rk3288_vpu_dec_run_done,
+static const struct rockchip_vpu_run_ops rockchip_vpu_dec_run_ops = {
+ .prepare_run = rockchip_vpu_dec_prepare_run,
+ .run_done = rockchip_vpu_dec_run_done,
};
-int rk3288_vpu_dec_init(struct rk3288_vpu_ctx *ctx)
+int rockchip_vpu_dec_init(struct rockchip_vpu_ctx *ctx)
{
ctx->vpu_src_fmt = find_format(DEF_SRC_FMT_DEC, false);
ctx->vpu_dst_fmt = find_format(DEF_DST_FMT_DEC, true);
- ctx->run_ops = &rk3288_vpu_dec_run_ops;
+ ctx->run_ops = &rockchip_vpu_dec_run_ops;
- return rk3288_vpu_ctrls_setup(ctx, &rk3288_vpu_dec_ctrl_ops,
+ return rockchip_vpu_ctrls_setup(ctx, &rockchip_vpu_dec_ctrl_ops,
controls, ARRAY_SIZE(controls), NULL);
}
-void rk3288_vpu_dec_exit(struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_dec_exit(struct rockchip_vpu_ctx *ctx)
{
- rk3288_vpu_ctrls_delete(ctx);
+ rockchip_vpu_ctrls_delete(ctx);
}
struct vb2_ops *get_dec_queue_ops(void);
const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void);
-struct rk3288_vpu_fmt *get_dec_def_fmt(bool src);
-int rk3288_vpu_dec_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_dec_exit(struct rk3288_vpu_ctx *ctx);
+struct rockchip_vpu_fmt *get_dec_def_fmt(bool src);
+int rockchip_vpu_dec_init(struct rockchip_vpu_ctx *ctx);
+void rockchip_vpu_dec_exit(struct rockchip_vpu_ctx *ctx);
#endif /* ROCKCHIP_VPU_DEC_H_ */
#define DEF_SRC_FMT_ENC V4L2_PIX_FMT_NV12
#define DEF_DST_FMT_ENC V4L2_PIX_FMT_VP8
-#define RK3288_ENC_MIN_WIDTH 96U
-#define RK3288_ENC_MAX_WIDTH 1920U
-#define RK3288_ENC_MIN_HEIGHT 96U
-#define RK3288_ENC_MAX_HEIGHT 1088U
+#define ROCKCHIP_ENC_MIN_WIDTH 96U
+#define ROCKCHIP_ENC_MAX_WIDTH 1920U
+#define ROCKCHIP_ENC_MIN_HEIGHT 96U
+#define ROCKCHIP_ENC_MAX_HEIGHT 1088U
-#define V4L2_CID_PRIVATE_RK3288_HEADER (V4L2_CID_CUSTOM_BASE + 0)
-#define V4L2_CID_PRIVATE_RK3288_REG_PARAMS (V4L2_CID_CUSTOM_BASE + 1)
-#define V4L2_CID_PRIVATE_RK3288_HW_PARAMS (V4L2_CID_CUSTOM_BASE + 2)
-#define V4L2_CID_PRIVATE_RK3288_RET_PARAMS (V4L2_CID_CUSTOM_BASE + 3)
+#define V4L2_CID_PRIVATE_ROCKCHIP_HEADER (V4L2_CID_CUSTOM_BASE + 0)
+#define V4L2_CID_PRIVATE_ROCKCHIP_REG_PARAMS (V4L2_CID_CUSTOM_BASE + 1)
+#define V4L2_CID_PRIVATE_ROCKCHIP_HW_PARAMS (V4L2_CID_CUSTOM_BASE + 2)
+#define V4L2_CID_PRIVATE_ROCKCHIP_RET_PARAMS (V4L2_CID_CUSTOM_BASE + 3)
-static struct rk3288_vpu_fmt formats[] = {
+static struct rockchip_vpu_fmt formats[] = {
/* Source formats. */
{
.name = "4:2:0 3 planes Y/Cb/Cr",
.codec_mode = RK_VPU_CODEC_NONE,
.num_planes = 3,
.depth = { 8, 4, 4 },
- .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
},
{
.name = "4:2:0 2 plane Y/CbCr",
.codec_mode = RK_VPU_CODEC_NONE,
.num_planes = 2,
.depth = { 8, 8 },
- .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
},
{
.name = "4:2:2 1 plane YUYV",
.codec_mode = RK_VPU_CODEC_NONE,
.num_planes = 1,
.depth = { 16 },
- .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
},
{
.name = "4:2:2 1 plane UYVY",
.codec_mode = RK_VPU_CODEC_NONE,
.num_planes = 1,
.depth = { 16 },
- .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
+ .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
},
/* Destination formats. */
{
.name = "VP8 Encoded Stream",
.fourcc = V4L2_PIX_FMT_VP8,
- .codec_mode = RK_VPU_CODEC_VP8E,
+ .codec_mode = RK3288_VPU_CODEC_VP8E,
.num_planes = 1,
},
};
-static struct rk3288_vpu_fmt *find_format(u32 fourcc, bool bitstream)
+static struct rockchip_vpu_fmt *find_format(u32 fourcc, bool bitstream)
{
unsigned int i;
* p_cur.p pointer of their v4l2_ctrl structs.
*/
enum {
- RK3288_VPU_ENC_CTRL_HEADER,
- RK3288_VPU_ENC_CTRL_REG_PARAMS,
- RK3288_VPU_ENC_CTRL_HW_PARAMS,
- RK3288_VPU_ENC_CTRL_RET_PARAMS,
+ ROCKCHIP_VPU_ENC_CTRL_HEADER,
+ ROCKCHIP_VPU_ENC_CTRL_REG_PARAMS,
+ ROCKCHIP_VPU_ENC_CTRL_HW_PARAMS,
+ ROCKCHIP_VPU_ENC_CTRL_RET_PARAMS,
};
-static struct rk3288_vpu_control controls[] = {
+static struct rockchip_vpu_control controls[] = {
/* Private, per-frame controls. */
- [RK3288_VPU_ENC_CTRL_HEADER] = {
- .id = V4L2_CID_PRIVATE_RK3288_HEADER,
+ [ROCKCHIP_VPU_ENC_CTRL_HEADER] = {
+ .id = V4L2_CID_PRIVATE_ROCKCHIP_HEADER,
.type = V4L2_CTRL_TYPE_PRIVATE,
- .name = "Rk3288 Private Header",
- .elem_size = RK3288_HEADER_SIZE,
+ .name = "Rockchip Private Header",
+ .elem_size = ROCKCHIP_HEADER_SIZE,
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_ENC_CTRL_REG_PARAMS] = {
- .id = V4L2_CID_PRIVATE_RK3288_REG_PARAMS,
+ [ROCKCHIP_VPU_ENC_CTRL_REG_PARAMS] = {
+ .id = V4L2_CID_PRIVATE_ROCKCHIP_REG_PARAMS,
.type = V4L2_CTRL_TYPE_PRIVATE,
- .name = "Rk3288 Private Reg Params",
- .elem_size = sizeof(struct rk3288_vp8e_reg_params),
+ .name = "Rockchip Private Reg Params",
+ .elem_size = sizeof(struct rockchip_reg_params),
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_ENC_CTRL_HW_PARAMS] = {
- .id = V4L2_CID_PRIVATE_RK3288_HW_PARAMS,
+ [ROCKCHIP_VPU_ENC_CTRL_HW_PARAMS] = {
+ .id = V4L2_CID_PRIVATE_ROCKCHIP_HW_PARAMS,
.type = V4L2_CTRL_TYPE_PRIVATE,
- .name = "Rk3288 Private Hw Params",
- .elem_size = RK3288_HW_PARAMS_SIZE,
+ .name = "Rockchip Private Hw Params",
+ .elem_size = ROCKCHIP_HW_PARAMS_SIZE,
.max_stores = VIDEO_MAX_FRAME,
.can_store = true,
},
- [RK3288_VPU_ENC_CTRL_RET_PARAMS] = {
- .id = V4L2_CID_PRIVATE_RK3288_RET_PARAMS,
+ [ROCKCHIP_VPU_ENC_CTRL_RET_PARAMS] = {
+ .id = V4L2_CID_PRIVATE_ROCKCHIP_RET_PARAMS,
.type = V4L2_CTRL_TYPE_PRIVATE,
- .name = "Rk3288 Private Ret Params",
+ .name = "Rockchip Private Ret Params",
.is_volatile = true,
.is_read_only = true,
.max_stores = VIDEO_MAX_FRAME,
- .elem_size = RK3288_RET_PARAMS_SIZE,
+ .elem_size = ROCKCHIP_RET_PARAMS_SIZE,
},
/* Generic controls. (currently ignored) */
{
},
};
-static inline const void *get_ctrl_ptr(struct rk3288_vpu_ctx *ctx, unsigned id)
+static inline const void *get_ctrl_ptr(struct rockchip_vpu_ctx *ctx, unsigned id)
{
struct v4l2_ctrl *ctrl = ctx->ctrls[id];
return ctrl->p_cur.p;
}
-static const char *const *rk3288_vpu_enc_get_menu(u32 id)
+static const char *const *rockchip_vpu_enc_get_menu(u32 id)
{
static const char *const vpu_video_frame_skip[] = {
"Disabled",
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
- struct rk3288_vpu_dev *dev = video_drvdata(file);
+ struct rockchip_vpu_dev *dev = video_drvdata(file);
vpu_debug_enter();
- strlcpy(cap->driver, RK3288_VPU_ENC_NAME, sizeof(cap->driver));
+ strlcpy(cap->driver, ROCKCHIP_VPU_ENC_NAME, sizeof(cap->driver));
strlcpy(cap->card, dev->pdev->name, sizeof(cap->card));
- strlcpy(cap->bus_info, "platform:" RK3288_VPU_NAME,
+ strlcpy(cap->bus_info, "platform:" ROCKCHIP_VPU_NAME,
sizeof(cap->bus_info));
/*
struct v4l2_frmsizeenum *fsize)
{
struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
if (fsize->index != 0) {
vpu_debug(0, "invalid frame size index (expected 0, got %d)\n",
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
- s->min_width = RK3288_ENC_MIN_WIDTH;
- s->max_width = RK3288_ENC_MAX_WIDTH;
+ s->min_width = ROCKCHIP_ENC_MIN_WIDTH;
+ s->max_width = ROCKCHIP_ENC_MAX_WIDTH;
s->step_width = MB_DIM;
- s->min_height = RK3288_ENC_MIN_HEIGHT;
- s->max_height = RK3288_ENC_MAX_HEIGHT;
+ s->min_height = ROCKCHIP_ENC_MIN_HEIGHT;
+ s->max_height = ROCKCHIP_ENC_MAX_HEIGHT;
s->step_height = MB_DIM;
return 0;
static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool out)
{
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
int i, j = 0;
vpu_debug_enter();
static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
vpu_debug_enter();
static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
char str[5];
/* Limit to hardware min/max. */
pix_fmt_mp->width = clamp(pix_fmt_mp->width,
- RK3288_ENC_MIN_WIDTH, RK3288_ENC_MAX_WIDTH);
+ ROCKCHIP_ENC_MIN_WIDTH, ROCKCHIP_ENC_MAX_WIDTH);
pix_fmt_mp->height = clamp(pix_fmt_mp->height,
- RK3288_ENC_MIN_HEIGHT, RK3288_ENC_MAX_HEIGHT);
+ ROCKCHIP_ENC_MIN_HEIGHT, ROCKCHIP_ENC_MAX_HEIGHT);
/* Round up to macroblocks. */
pix_fmt_mp->width = round_up(pix_fmt_mp->width, MB_DIM);
pix_fmt_mp->height = round_up(pix_fmt_mp->height, MB_DIM);
return 0;
}
-static void calculate_plane_sizes(struct rk3288_vpu_fmt *fmt,
+static void calculate_plane_sizes(struct rockchip_vpu_fmt *fmt,
unsigned int w, unsigned int h,
struct v4l2_pix_format_mplane *pix_fmt_mp)
{
static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
unsigned int mb_width, mb_height;
- struct rk3288_vpu_fmt *fmt;
+ struct rockchip_vpu_fmt *fmt;
int ret = 0;
vpu_debug_enter();
static int vidioc_reqbufs(struct file *file, void *priv,
struct v4l2_requestbuffers *reqbufs)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_querybuf(struct file *file, void *priv,
struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
int i;
static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_expbuf(struct file *file, void *priv,
struct v4l2_exportbuffer *eb)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
static int vidioc_streamoff(struct file *file, void *priv,
enum v4l2_buf_type type)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret;
vpu_debug_enter();
return ret;
}
-static int rk3288_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
+static int rockchip_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
{
- struct rk3288_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
+ struct rockchip_vpu_dev *dev = ctx->dev;
int ret = 0;
vpu_debug_enter();
/* Ignore these controls for now. (FIXME?) */
break;
- case V4L2_CID_PRIVATE_RK3288_HEADER:
- case V4L2_CID_PRIVATE_RK3288_REG_PARAMS:
- case V4L2_CID_PRIVATE_RK3288_HW_PARAMS:
+ case V4L2_CID_PRIVATE_ROCKCHIP_HEADER:
+ case V4L2_CID_PRIVATE_ROCKCHIP_REG_PARAMS:
+ case V4L2_CID_PRIVATE_ROCKCHIP_HW_PARAMS:
/* Nothing to do here. The control is used directly. */
break;
return ret;
}
-static int rk3288_vpu_enc_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+static int rockchip_vpu_enc_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
- struct rk3288_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_ctx *ctx = ctrl_to_ctx(ctrl);
+ struct rockchip_vpu_dev *dev = ctx->dev;
int ret = 0;
vpu_debug_enter();
vpu_debug(4, "ctrl id %d\n", ctrl->id);
switch (ctrl->id) {
- case V4L2_CID_PRIVATE_RK3288_RET_PARAMS:
+ case V4L2_CID_PRIVATE_ROCKCHIP_RET_PARAMS:
memcpy(ctrl->p_new.p, ctx->run.priv_dst.cpu,
- RK3288_RET_PARAMS_SIZE);
+ ROCKCHIP_RET_PARAMS_SIZE);
break;
default:
return ret;
}
-static const struct v4l2_ctrl_ops rk3288_vpu_enc_ctrl_ops = {
- .s_ctrl = rk3288_vpu_enc_s_ctrl,
- .g_volatile_ctrl = rk3288_vpu_enc_g_volatile_ctrl,
+static const struct v4l2_ctrl_ops rockchip_vpu_enc_ctrl_ops = {
+ .s_ctrl = rockchip_vpu_enc_s_ctrl,
+ .g_volatile_ctrl = rockchip_vpu_enc_g_volatile_ctrl,
};
static int vidioc_cropcap(struct file *file, void *priv,
struct v4l2_cropcap *cap)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
struct v4l2_pix_format_mplane *fmt = &ctx->src_fmt;
int ret = 0;
static int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
int ret = 0;
vpu_debug_enter();
static int vidioc_s_crop(struct file *file, void *priv,
const struct v4l2_crop *crop)
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv);
struct v4l2_pix_format_mplane *fmt = &ctx->src_fmt;
const struct v4l2_rect *rect = &crop->c;
int ret = 0;
return ret;
}
-static const struct v4l2_ioctl_ops rk3288_vpu_enc_ioctl_ops = {
+static const struct v4l2_ioctl_ops rockchip_vpu_enc_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_framesizes = vidioc_enum_framesizes,
.vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
.vidioc_s_crop = vidioc_s_crop,
};
-static int rk3288_vpu_queue_setup(struct vb2_queue *vq,
+static int rockchip_vpu_queue_setup(struct vb2_queue *vq,
const void *parg,
unsigned int *buf_count,
unsigned int *plane_count,
unsigned int psize[], void *allocators[])
{
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
int ret = 0;
int i;
return ret;
}
-static int rk3288_vpu_buf_prepare(struct vb2_buffer *vb)
+static int rockchip_vpu_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
int ret = 0;
int i;
return ret;
}
-static void rk3288_vpu_buf_finish(struct vb2_buffer *vb)
+static void rockchip_vpu_buf_finish(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
vpu_debug_enter();
if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
&& vb->state == VB2_BUF_STATE_DONE
&& ctx->vpu_dst_fmt->fourcc == V4L2_PIX_FMT_VP8) {
- struct rk3288_vpu_buf *buf;
+ struct rockchip_vpu_buf *buf;
buf = vb_to_buf(vb);
rk3288_vpu_vp8e_assemble_bitstream(ctx, buf);
vpu_debug_leave();
}
-static int rk3288_vpu_start_streaming(struct vb2_queue *q, unsigned int count)
+static int rockchip_vpu_start_streaming(struct vb2_queue *q, unsigned int count)
{
int ret = 0;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
bool ready = false;
vpu_debug_enter();
if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
- ret = rk3288_vpu_init(ctx);
+ ret = rockchip_vpu_init(ctx);
if (ret < 0) {
- vpu_err("rk3288_vpu_init failed\n");
+ vpu_err("rockchip_vpu_init failed\n");
return ret;
}
}
if (ready)
- rk3288_vpu_try_context(dev, ctx);
+ rockchip_vpu_try_context(dev, ctx);
vpu_debug_leave();
return 0;
}
-static void rk3288_vpu_stop_streaming(struct vb2_queue *q)
+static void rockchip_vpu_stop_streaming(struct vb2_queue *q)
{
unsigned long flags;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
- struct rk3288_vpu_buf *b;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(q->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_buf *b;
LIST_HEAD(queue);
int i;
wait_event(dev->run_wq, dev->current_ctx != ctx);
while (!list_empty(&queue)) {
- b = list_first_entry(&queue, struct rk3288_vpu_buf, list);
+ b = list_first_entry(&queue, struct rockchip_vpu_buf, list);
for (i = 0; i < b->vb.vb2_buf.num_planes; i++)
vb2_set_plane_payload(&b->vb.vb2_buf, i, 0);
vb2_buffer_done(&b->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
- rk3288_vpu_deinit(ctx);
+ rockchip_vpu_deinit(ctx);
vpu_debug_leave();
}
-static void rk3288_vpu_buf_queue(struct vb2_buffer *vb)
+static void rockchip_vpu_buf_queue(struct vb2_buffer *vb)
{
struct vb2_queue *vq = vb->vb2_queue;
- struct rk3288_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
- struct rk3288_vpu_dev *dev = ctx->dev;
- struct rk3288_vpu_buf *vpu_buf;
+ struct rockchip_vpu_ctx *ctx = fh_to_ctx(vq->drv_priv);
+ struct rockchip_vpu_dev *dev = ctx->dev;
+ struct rockchip_vpu_buf *vpu_buf;
unsigned long flags;
vpu_debug_enter();
}
if (vb2_is_streaming(&ctx->vq_src) && vb2_is_streaming(&ctx->vq_dst))
- rk3288_vpu_try_context(dev, ctx);
+ rockchip_vpu_try_context(dev, ctx);
vpu_debug_leave();
}
-static struct vb2_ops rk3288_vpu_enc_qops = {
- .queue_setup = rk3288_vpu_queue_setup,
+static struct vb2_ops rockchip_vpu_enc_qops = {
+ .queue_setup = rockchip_vpu_queue_setup,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
- .buf_prepare = rk3288_vpu_buf_prepare,
- .buf_finish = rk3288_vpu_buf_finish,
- .start_streaming = rk3288_vpu_start_streaming,
- .stop_streaming = rk3288_vpu_stop_streaming,
- .buf_queue = rk3288_vpu_buf_queue,
+ .buf_prepare = rockchip_vpu_buf_prepare,
+ .buf_finish = rockchip_vpu_buf_finish,
+ .start_streaming = rockchip_vpu_start_streaming,
+ .stop_streaming = rockchip_vpu_stop_streaming,
+ .buf_queue = rockchip_vpu_buf_queue,
};
struct vb2_ops *get_enc_queue_ops(void)
{
- return &rk3288_vpu_enc_qops;
+ return &rockchip_vpu_enc_qops;
}
const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void)
{
- return &rk3288_vpu_enc_ioctl_ops;
+ return &rockchip_vpu_enc_ioctl_ops;
}
-static void rk3288_vpu_enc_prepare_run(struct rk3288_vpu_ctx *ctx)
+static void rockchip_vpu_enc_prepare_run(struct rockchip_vpu_ctx *ctx)
{
struct vb2_v4l2_buffer *vb2_src = to_vb2_v4l2_buffer(&ctx->run.src->vb.vb2_buf);
unsigned config_store = vb2_src->config_store;
v4l2_ctrl_apply_store(&ctx->ctrl_handler, config_store);
memcpy(ctx->run.dst->vp8e.header,
- get_ctrl_ptr(ctx, RK3288_VPU_ENC_CTRL_HEADER),
- RK3288_HEADER_SIZE);
+ get_ctrl_ptr(ctx, ROCKCHIP_VPU_ENC_CTRL_HEADER),
+ ROCKCHIP_HEADER_SIZE);
ctx->run.vp8e.reg_params = get_ctrl_ptr(ctx,
- RK3288_VPU_ENC_CTRL_REG_PARAMS);
+ ROCKCHIP_VPU_ENC_CTRL_REG_PARAMS);
memcpy(ctx->run.priv_src.cpu,
- get_ctrl_ptr(ctx, RK3288_VPU_ENC_CTRL_HW_PARAMS),
- RK3288_HW_PARAMS_SIZE);
+ get_ctrl_ptr(ctx, ROCKCHIP_VPU_ENC_CTRL_HW_PARAMS),
+ ROCKCHIP_HW_PARAMS_SIZE);
}
-static const struct rk3288_vpu_run_ops rk3288_vpu_enc_run_ops = {
- .prepare_run = rk3288_vpu_enc_prepare_run,
+static const struct rockchip_vpu_run_ops rockchip_vpu_enc_run_ops = {
+ .prepare_run = rockchip_vpu_enc_prepare_run,
};
-int rk3288_vpu_enc_init(struct rk3288_vpu_ctx *ctx)
+int rockchip_vpu_enc_init(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
int ret;
ctx->vpu_src_fmt = find_format(DEF_SRC_FMT_ENC, false);
ctx->vpu_dst_fmt = find_format(DEF_DST_FMT_ENC, true);
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->run.priv_src,
- RK3288_HW_PARAMS_SIZE);
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->run.priv_src,
+ ROCKCHIP_HW_PARAMS_SIZE);
if (ret) {
vpu_err("Failed to allocate private source buffer.\n");
return ret;
}
- ret = rk3288_vpu_aux_buf_alloc(vpu, &ctx->run.priv_dst,
- RK3288_RET_PARAMS_SIZE);
+ ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->run.priv_dst,
+ ROCKCHIP_RET_PARAMS_SIZE);
if (ret) {
vpu_err("Failed to allocate private destination buffer.\n");
goto err_priv_src;
}
- ret = rk3288_vpu_ctrls_setup(ctx, &rk3288_vpu_enc_ctrl_ops,
+ ret = rockchip_vpu_ctrls_setup(ctx, &rockchip_vpu_enc_ctrl_ops,
controls, ARRAY_SIZE(controls),
- rk3288_vpu_enc_get_menu);
+ rockchip_vpu_enc_get_menu);
if (ret) {
vpu_err("Failed to set up controls\n");
goto err_priv_dst;
}
- ctx->run_ops = &rk3288_vpu_enc_run_ops;
+ ctx->run_ops = &rockchip_vpu_enc_run_ops;
return 0;
err_priv_dst:
- rk3288_vpu_aux_buf_free(vpu, &ctx->run.priv_dst);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->run.priv_dst);
err_priv_src:
- rk3288_vpu_aux_buf_free(vpu, &ctx->run.priv_src);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->run.priv_src);
return ret;
}
-void rk3288_vpu_enc_exit(struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_enc_exit(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
- rk3288_vpu_ctrls_delete(ctx);
+ rockchip_vpu_ctrls_delete(ctx);
- rk3288_vpu_aux_buf_free(vpu, &ctx->run.priv_dst);
- rk3288_vpu_aux_buf_free(vpu, &ctx->run.priv_src);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->run.priv_dst);
+ rockchip_vpu_aux_buf_free(vpu, &ctx->run.priv_src);
};
/*
* WAR for encoder state corruption after decoding
*/
-static const struct rk3288_vpu_run_ops dummy_encode_run_ops = {
+static const struct rockchip_vpu_run_ops dummy_encode_run_ops = {
/* No ops needed for dummy encoding. */
};
#define DUMMY_DST_FMT V4L2_PIX_FMT_VP8
#define DUMMY_DST_SIZE (32 * 1024)
-int rk3288_vpu_enc_init_dummy_ctx(struct rk3288_vpu_dev *dev)
+int rockchip_vpu_enc_init_dummy_ctx(struct rockchip_vpu_dev *dev)
{
- struct rk3288_vpu_ctx *ctx;
+ struct rockchip_vpu_ctx *ctx;
int ret;
int i;
INIT_LIST_HEAD(&ctx->dst_queue);
INIT_LIST_HEAD(&ctx->list);
- ctx->run.vp8e.reg_params = rk3288_vpu_vp8e_get_dummy_params();
+ ctx->run.vp8e.reg_params =
+ rk3288_vpu_vp8e_get_dummy_params();
ctx->run_ops = &dummy_encode_run_ops;
ctx->run.dst = devm_kzalloc(dev->dev, sizeof(*ctx->run.dst),
if (!ctx->run.dst)
return -ENOMEM;
- ret = rk3288_vpu_aux_buf_alloc(dev, &ctx->run.priv_src,
- RK3288_HW_PARAMS_SIZE);
+ ret = rockchip_vpu_aux_buf_alloc(dev, &ctx->run.priv_src,
+ ROCKCHIP_HW_PARAMS_SIZE);
if (ret)
return ret;
- ret = rk3288_vpu_aux_buf_alloc(dev, &ctx->run.priv_dst,
- RK3288_RET_PARAMS_SIZE);
+ ret = rockchip_vpu_aux_buf_alloc(dev, &ctx->run.priv_dst,
+ ROCKCHIP_RET_PARAMS_SIZE);
if (ret)
goto err_free_priv_src;
for (i = 0; i < ctx->src_fmt.num_planes; ++i) {
- ret = rk3288_vpu_aux_buf_alloc(dev, &dev->dummy_encode_src[i],
+ ret = rockchip_vpu_aux_buf_alloc(dev, &dev->dummy_encode_src[i],
ctx->src_fmt.plane_fmt[i].sizeimage);
if (ret)
goto err_free_src;
dev->dummy_encode_src[i].size);
}
- ret = rk3288_vpu_aux_buf_alloc(dev, &dev->dummy_encode_dst,
+ ret = rockchip_vpu_aux_buf_alloc(dev, &dev->dummy_encode_dst,
ctx->dst_fmt.plane_fmt[0].sizeimage);
if (ret)
goto err_free_src;
memset(dev->dummy_encode_dst.cpu, 0, dev->dummy_encode_dst.size);
- ret = rk3288_vpu_init(ctx);
+ ret = rockchip_vpu_init(ctx);
if (ret)
goto err_free_dst;
return 0;
err_free_dst:
- rk3288_vpu_aux_buf_free(dev, &dev->dummy_encode_dst);
+ rockchip_vpu_aux_buf_free(dev, &dev->dummy_encode_dst);
err_free_src:
for (i = 0; i < ctx->src_fmt.num_planes; ++i)
if (dev->dummy_encode_src[i].cpu)
- rk3288_vpu_aux_buf_free(dev, &dev->dummy_encode_src[i]);
- rk3288_vpu_aux_buf_free(dev, &ctx->run.priv_dst);
+ rockchip_vpu_aux_buf_free(dev, &dev->dummy_encode_src[i]);
+ rockchip_vpu_aux_buf_free(dev, &ctx->run.priv_dst);
err_free_priv_src:
- rk3288_vpu_aux_buf_free(dev, &ctx->run.priv_src);
+ rockchip_vpu_aux_buf_free(dev, &ctx->run.priv_src);
return ret;
}
-void rk3288_vpu_enc_free_dummy_ctx(struct rk3288_vpu_dev *dev)
+void rockchip_vpu_enc_free_dummy_ctx(struct rockchip_vpu_dev *dev)
{
- struct rk3288_vpu_ctx *ctx = dev->dummy_encode_ctx;
+ struct rockchip_vpu_ctx *ctx = dev->dummy_encode_ctx;
int i;
- rk3288_vpu_deinit(ctx);
+ rockchip_vpu_deinit(ctx);
for (i = 0; i < ctx->src_fmt.num_planes; ++i)
- rk3288_vpu_aux_buf_free(dev, &dev->dummy_encode_src[i]);
- rk3288_vpu_aux_buf_free(dev, &dev->dummy_encode_dst);
- rk3288_vpu_aux_buf_free(dev, &ctx->run.priv_src);
- rk3288_vpu_aux_buf_free(dev, &ctx->run.priv_dst);
+ rockchip_vpu_aux_buf_free(dev, &dev->dummy_encode_src[i]);
+ rockchip_vpu_aux_buf_free(dev, &dev->dummy_encode_dst);
+ rockchip_vpu_aux_buf_free(dev, &ctx->run.priv_src);
+ rockchip_vpu_aux_buf_free(dev, &ctx->run.priv_dst);
}
struct vb2_ops *get_enc_queue_ops(void);
const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void);
-struct rk3288_vpu_fmt *get_enc_def_fmt(bool src);
-int rk3288_vpu_enc_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_enc_exit(struct rk3288_vpu_ctx *ctx);
-int rk3288_vpu_enc_init_dummy_ctx(struct rk3288_vpu_dev *dev);
-void rk3288_vpu_enc_free_dummy_ctx(struct rk3288_vpu_dev *dev);
+struct rockchip_vpu_fmt *get_enc_def_fmt(bool src);
+int rockchip_vpu_enc_init(struct rockchip_vpu_ctx *ctx);
+void rockchip_vpu_enc_exit(struct rockchip_vpu_ctx *ctx);
+int rockchip_vpu_enc_init_dummy_ctx(struct rockchip_vpu_dev *dev);
+void rockchip_vpu_enc_free_dummy_ctx(struct rockchip_vpu_dev *dev);
#endif /* ROCKCHIP_VPU_ENC_H_ */
#include "rk3288_vpu_regs.h"
/**
- * struct rk3288_vpu_variant - information about VPU hardware variant
+ * struct rockchip_vpu_variant - information about VPU hardware variant
*
* @hw_id: Top 16 bits (product ID) of hardware ID register.
* @enc_offset: Offset from VPU base to encoder registers.
* @dec_offset: Offset from VPU base to decoder registers.
* @dec_reg_num: Number of registers of decoder block.
*/
-struct rk3288_vpu_variant {
+struct rockchip_vpu_variant {
u16 hw_id;
unsigned enc_offset;
unsigned enc_reg_num;
};
/* Supported VPU variants. */
-static const struct rk3288_vpu_variant rk3288_vpu_variants[] = {
+static const struct rockchip_vpu_variant rockchip_vpu_variants[] = {
{
.hw_id = 0x4831,
.enc_offset = 0x0,
};
/**
- * struct rk3288_vpu_codec_ops - codec mode specific operations
+ * struct rockchip_vpu_codec_ops - codec mode specific operations
*
* @init: Prepare for streaming. Called from VB2 .start_streaming()
* when streaming from both queues is being enabled.
* @done: Read back processing results and additional data from hardware.
* @reset: Reset the hardware in case of a timeout.
*/
-struct rk3288_vpu_codec_ops {
- int (*init)(struct rk3288_vpu_ctx *);
- void (*exit)(struct rk3288_vpu_ctx *);
+struct rockchip_vpu_codec_ops {
+ int (*init)(struct rockchip_vpu_ctx *);
+ void (*exit)(struct rockchip_vpu_ctx *);
- void (*run)(struct rk3288_vpu_ctx *);
- void (*done)(struct rk3288_vpu_ctx *, enum vb2_buffer_state);
- void (*reset)(struct rk3288_vpu_ctx *);
+ void (*run)(struct rockchip_vpu_ctx *);
+ void (*done)(struct rockchip_vpu_ctx *, enum vb2_buffer_state);
+ void (*reset)(struct rockchip_vpu_ctx *);
};
/*
* Hardware control routines.
*/
-static int rk3288_vpu_identify(struct rk3288_vpu_dev *vpu)
+static int rockchip_vpu_identify(struct rockchip_vpu_dev *vpu)
{
u32 hw_id;
int i;
dev_info(vpu->dev, "Read hardware ID: %x\n", hw_id);
- for (i = 0; i < ARRAY_SIZE(rk3288_vpu_variants); ++i) {
- if (hw_id == rk3288_vpu_variants[i].hw_id) {
- vpu->variant = &rk3288_vpu_variants[i];
+ for (i = 0; i < ARRAY_SIZE(rockchip_vpu_variants); ++i) {
+ if (hw_id == rockchip_vpu_variants[i].hw_id) {
+ vpu->variant = &rockchip_vpu_variants[i];
return 0;
}
}
return -ENOENT;
}
-void rk3288_vpu_power_on(struct rk3288_vpu_dev *vpu)
+void rockchip_vpu_power_on(struct rockchip_vpu_dev *vpu)
{
vpu_debug_enter();
vpu_debug_leave();
}
-static void rk3288_vpu_power_off(struct rk3288_vpu_dev *vpu)
+static void rockchip_vpu_power_off(struct rockchip_vpu_dev *vpu)
{
vpu_debug_enter();
static irqreturn_t vepu_irq(int irq, void *dev_id)
{
- struct rk3288_vpu_dev *vpu = dev_id;
+ struct rockchip_vpu_dev *vpu = dev_id;
u32 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
if (status & VEPU_REG_INTERRUPT_BIT) {
- struct rk3288_vpu_ctx *ctx = vpu->current_ctx;
+ struct rockchip_vpu_ctx *ctx = vpu->current_ctx;
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
- rk3288_vpu_power_off(vpu);
+ rockchip_vpu_power_off(vpu);
cancel_delayed_work(&vpu->watchdog_work);
ctx->hw.codec_ops->done(ctx, VB2_BUF_STATE_DONE);
static irqreturn_t vdpu_irq(int irq, void *dev_id)
{
- struct rk3288_vpu_dev *vpu = dev_id;
+ struct rockchip_vpu_dev *vpu = dev_id;
u32 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
vpu_debug(3, "vdpu_irq status: %08x\n", status);
if (status & VDPU_REG_INTERRUPT_DEC_IRQ) {
- struct rk3288_vpu_ctx *ctx = vpu->current_ctx;
+ struct rockchip_vpu_ctx *ctx = vpu->current_ctx;
vdpu_write(vpu, 0, VDPU_REG_CONFIG);
- rk3288_vpu_power_off(vpu);
+ rockchip_vpu_power_off(vpu);
cancel_delayed_work(&vpu->watchdog_work);
ctx->hw.codec_ops->done(ctx, VB2_BUF_STATE_DONE);
return IRQ_HANDLED;
}
-static void rk3288_vpu_watchdog(struct work_struct *work)
+static void rockchip_vpu_watchdog(struct work_struct *work)
{
- struct rk3288_vpu_dev *vpu = container_of(to_delayed_work(work),
- struct rk3288_vpu_dev, watchdog_work);
- struct rk3288_vpu_ctx *ctx = vpu->current_ctx;
+ struct rockchip_vpu_dev *vpu = container_of(to_delayed_work(work),
+ struct rockchip_vpu_dev, watchdog_work);
+ struct rockchip_vpu_ctx *ctx = vpu->current_ctx;
unsigned long flags;
spin_lock_irqsave(&vpu->irqlock, flags);
vpu_err("frame processing timed out!\n");
- rk3288_vpu_power_off(vpu);
+ rockchip_vpu_power_off(vpu);
ctx->hw.codec_ops->done(ctx, VB2_BUF_STATE_ERROR);
}
*/
#if defined(CONFIG_ROCKCHIP_IOMMU)
-static int rk3288_vpu_iommu_init(struct rk3288_vpu_dev *vpu)
+static int rockchip_vpu_iommu_init(struct rockchip_vpu_dev *vpu)
{
int ret;
return ret;
}
-static void rk3288_vpu_iommu_cleanup(struct rk3288_vpu_dev *vpu)
+static void rockchip_vpu_iommu_cleanup(struct rockchip_vpu_dev *vpu)
{
iommu_detach_device(vpu->domain, vpu->dev);
iommu_put_dma_cookie(vpu->domain);
iommu_domain_free(vpu->domain);
}
#else /* CONFIG_ROCKCHIP_IOMMU */
-static inline int rk3288_vpu_iommu_init(struct rk3288_vpu_dev *vpu)
+static inline int rockchip_vpu_iommu_init(struct rockchip_vpu_dev *vpu)
{
return 0;
}
-static inline void rk3288_vpu_iommu_cleanup(struct rk3288_vpu_dev *vpu) { }
+static inline void rockchip_vpu_iommu_cleanup(struct rockchip_vpu_dev *vpu) { }
#endif /* CONFIG_ROCKCHIP_IOMMU */
-int rk3288_vpu_hw_probe(struct rk3288_vpu_dev *vpu)
+int rockchip_vpu_hw_probe(struct rockchip_vpu_dev *vpu)
{
struct resource *res;
int irq_enc, irq_dec;
pr_info("probe device %s\n", dev_name(vpu->dev));
- INIT_DELAYED_WORK(&vpu->watchdog_work, rk3288_vpu_watchdog);
+ INIT_DELAYED_WORK(&vpu->watchdog_work, rockchip_vpu_watchdog);
vpu->aclk_vcodec = devm_clk_get(vpu->dev, "aclk_vcodec");
if (IS_ERR(vpu->aclk_vcodec)) {
clk_prepare_enable(vpu->aclk_vcodec);
clk_prepare_enable(vpu->hclk_vcodec);
- ret = rk3288_vpu_identify(vpu);
+ ret = rockchip_vpu_identify(vpu);
if (ret < 0) {
dev_err(vpu->dev, "failed to identify hardware variant\n");
goto err_power;
goto err_power;
}
- ret = rk3288_vpu_iommu_init(vpu);
+ ret = rockchip_vpu_iommu_init(vpu);
if (ret)
goto err_power;
return 0;
err_iommu:
- rk3288_vpu_iommu_cleanup(vpu);
+ rockchip_vpu_iommu_cleanup(vpu);
err_power:
clk_disable_unprepare(vpu->hclk_vcodec);
clk_disable_unprepare(vpu->aclk_vcodec);
return ret;
}
-void rk3288_vpu_hw_remove(struct rk3288_vpu_dev *vpu)
+void rockchip_vpu_hw_remove(struct rockchip_vpu_dev *vpu)
{
- rk3288_vpu_iommu_cleanup(vpu);
+ rockchip_vpu_iommu_cleanup(vpu);
pm_runtime_disable(vpu->dev);
clk_disable_unprepare(vpu->aclk_vcodec);
}
-static void rk3288_vpu_enc_reset(struct rk3288_vpu_ctx *ctx)
+static void rockchip_vpu_enc_reset(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_ENC_CTRL);
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
}
-static void rk3288_vpu_dec_reset(struct rk3288_vpu_ctx *ctx)
+static void rockchip_vpu_dec_reset(struct rockchip_vpu_ctx *ctx)
{
- struct rk3288_vpu_dev *vpu = ctx->dev;
+ struct rockchip_vpu_dev *vpu = ctx->dev;
vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
vdpu_write(vpu, 0, VDPU_REG_CONFIG);
}
-static const struct rk3288_vpu_codec_ops mode_ops[] = {
- [RK_VPU_CODEC_VP8E] = {
+static const struct rockchip_vpu_codec_ops mode_ops[] = {
+ [RK3288_VPU_CODEC_VP8E] = {
.init = rk3288_vpu_vp8e_init,
.exit = rk3288_vpu_vp8e_exit,
.run = rk3288_vpu_vp8e_run,
.done = rk3288_vpu_vp8e_done,
- .reset = rk3288_vpu_enc_reset,
+ .reset = rockchip_vpu_enc_reset,
},
- [RK_VPU_CODEC_VP8D] = {
+ [RK3288_VPU_CODEC_VP8D] = {
.init = rk3288_vpu_vp8d_init,
.exit = rk3288_vpu_vp8d_exit,
.run = rk3288_vpu_vp8d_run,
- .done = rk3288_vpu_run_done,
- .reset = rk3288_vpu_dec_reset,
+ .done = rockchip_vpu_run_done,
+ .reset = rockchip_vpu_dec_reset,
},
- [RK_VPU_CODEC_H264D] = {
+ [RK3288_VPU_CODEC_H264D] = {
.init = rk3288_vpu_h264d_init,
.exit = rk3288_vpu_h264d_exit,
.run = rk3288_vpu_h264d_run,
- .done = rk3288_vpu_run_done,
- .reset = rk3288_vpu_dec_reset,
+ .done = rockchip_vpu_run_done,
+ .reset = rockchip_vpu_dec_reset,
},
};
-void rk3288_vpu_run(struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_run(struct rockchip_vpu_ctx *ctx)
{
ctx->hw.codec_ops->run(ctx);
}
-int rk3288_vpu_init(struct rk3288_vpu_ctx *ctx)
+int rockchip_vpu_init(struct rockchip_vpu_ctx *ctx)
{
- enum rk3288_vpu_codec_mode codec_mode;
+ enum rockchip_vpu_codec_mode codec_mode;
- if (rk3288_vpu_ctx_is_encoder(ctx))
+ if (rockchip_vpu_ctx_is_encoder(ctx))
codec_mode = ctx->vpu_dst_fmt->codec_mode; /* Encoder */
else
codec_mode = ctx->vpu_src_fmt->codec_mode; /* Decoder */
return ctx->hw.codec_ops->init(ctx);
}
-void rk3288_vpu_deinit(struct rk3288_vpu_ctx *ctx)
+void rockchip_vpu_deinit(struct rockchip_vpu_ctx *ctx)
{
ctx->hw.codec_ops->exit(ctx);
}
#include <media/videobuf2-core.h>
-#define RK3288_HEADER_SIZE 1280
-#define RK3288_HW_PARAMS_SIZE 5487
-#define RK3288_RET_PARAMS_SIZE 488
+#define ROCKCHIP_HEADER_SIZE 1280
+#define ROCKCHIP_HW_PARAMS_SIZE 5487
+#define ROCKCHIP_RET_PARAMS_SIZE 488
-struct rk3288_vpu_dev;
-struct rk3288_vpu_ctx;
-struct rk3288_vpu_buf;
-
-struct rk3288_vpu_h264d_priv_tbl;
+struct rockchip_vpu_dev;
+struct rockchip_vpu_ctx;
+struct rockchip_vpu_buf;
/**
- * enum rk3288_vpu_enc_fmt - source format ID for hardware registers.
+ * enum rockchip_vpu_enc_fmt - source format ID for hardware registers.
*/
-enum rk3288_vpu_enc_fmt {
- RK3288_VPU_ENC_FMT_YUV420P = 0,
- RK3288_VPU_ENC_FMT_YUV420SP = 1,
- RK3288_VPU_ENC_FMT_YUYV422 = 2,
- RK3288_VPU_ENC_FMT_UYVY422 = 3,
+enum rockchip_vpu_enc_fmt {
+ ROCKCHIP_VPU_ENC_FMT_YUV420P = 0,
+ ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1,
+ ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2,
+ ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
};
/**
};
/**
- * struct rk3288_vpu_aux_buf - auxiliary DMA buffer for hardware data
+ * struct rockchip_reg_params - low level encoding parameters
+ */
+struct rockchip_reg_params {
+ /* Mode-specific data. */
+ union {
+ const struct rk3288_vp8e_reg_params rk3288_vp8e;
+ };
+};
+
+/**
+ * struct rockchip_vpu_aux_buf - auxiliary DMA buffer for hardware data
* @cpu: CPU pointer to the buffer.
* @dma: DMA address of the buffer.
* @size: Size of the buffer.
*/
-struct rk3288_vpu_aux_buf {
+struct rockchip_vpu_aux_buf {
void *cpu;
dma_addr_t dma;
size_t size;
};
/**
- * struct rk3288_vpu_vp8e_hw_ctx - Context private data specific to codec mode.
+ * struct rockchip_vpu_vp8e_hw_ctx - Context private data specific to codec mode.
* @ctrl_buf: VP8 control buffer.
* @ext_buf: VP8 ext data buffer.
* @mv_buf: VP8 motion vector buffer.
* @ref_rec_ptr: Bit flag for swapping ref and rec buffers every frame.
*/
-struct rk3288_vpu_vp8e_hw_ctx {
- struct rk3288_vpu_aux_buf ctrl_buf;
- struct rk3288_vpu_aux_buf ext_buf;
- struct rk3288_vpu_aux_buf mv_buf;
+struct rockchip_vpu_vp8e_hw_ctx {
+ struct rockchip_vpu_aux_buf ctrl_buf;
+ struct rockchip_vpu_aux_buf ext_buf;
+ struct rockchip_vpu_aux_buf mv_buf;
u8 ref_rec_ptr:1;
};
/**
- * struct rk3288_vpu_vp8d_hw_ctx - Context private data of VP8 decoder.
+ * struct rockchip_vpu_vp8d_hw_ctx - Context private data of VP8 decoder.
* @segment_map: Segment map buffer.
* @prob_tbl: Probability table buffer.
*/
-struct rk3288_vpu_vp8d_hw_ctx {
- struct rk3288_vpu_aux_buf segment_map;
- struct rk3288_vpu_aux_buf prob_tbl;
+struct rockchip_vpu_vp8d_hw_ctx {
+ struct rockchip_vpu_aux_buf segment_map;
+ struct rockchip_vpu_aux_buf prob_tbl;
};
/**
- * struct rk3288_vpu_h264d_hw_ctx - Per context data specific to H264 decoding.
+ * struct rockchip_vpu_h264d_hw_ctx - Per context data specific to H264 decoding.
* @priv_tbl: Private auxiliary buffer for hardware.
*/
-struct rk3288_vpu_h264d_hw_ctx {
- struct rk3288_vpu_aux_buf priv_tbl;
+struct rockchip_vpu_h264d_hw_ctx {
+ struct rockchip_vpu_aux_buf priv_tbl;
};
/**
- * struct rk3288_vpu_hw_ctx - Context private data of hardware code.
+ * struct rockchip_vpu_hw_ctx - Context private data of hardware code.
* @codec_ops: Set of operations associated with current codec mode.
*/
-struct rk3288_vpu_hw_ctx {
- const struct rk3288_vpu_codec_ops *codec_ops;
+struct rockchip_vpu_hw_ctx {
+ const struct rockchip_vpu_codec_ops *codec_ops;
/* Specific for particular codec modes. */
union {
- struct rk3288_vpu_vp8e_hw_ctx vp8e;
- struct rk3288_vpu_vp8d_hw_ctx vp8d;
- struct rk3288_vpu_h264d_hw_ctx h264d;
+ struct rockchip_vpu_vp8e_hw_ctx vp8e;
+ struct rockchip_vpu_vp8d_hw_ctx vp8d;
+ struct rockchip_vpu_h264d_hw_ctx h264d;
/* Other modes will need different data. */
};
};
-int rk3288_vpu_hw_probe(struct rk3288_vpu_dev *vpu);
-void rk3288_vpu_hw_remove(struct rk3288_vpu_dev *vpu);
+int rockchip_vpu_hw_probe(struct rockchip_vpu_dev *vpu);
+void rockchip_vpu_hw_remove(struct rockchip_vpu_dev *vpu);
+
+void rockchip_vpu_power_on(struct rockchip_vpu_dev *vpu);
-int rk3288_vpu_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_deinit(struct rk3288_vpu_ctx *ctx);
+int rockchip_vpu_init(struct rockchip_vpu_ctx *ctx);
+void rockchip_vpu_deinit(struct rockchip_vpu_ctx *ctx);
-void rk3288_vpu_run(struct rk3288_vpu_ctx *ctx);
+void rockchip_vpu_run(struct rockchip_vpu_ctx *ctx);
-/* Run ops for H264 decoder */
-int rk3288_vpu_h264d_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_h264d_exit(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_h264d_run(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_power_on(struct rk3288_vpu_dev *vpu);
+/* Run ops for rk3288 H264 decoder */
+int rk3288_vpu_h264d_init(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_h264d_exit(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_h264d_run(struct rockchip_vpu_ctx *ctx);
-/* Run ops for VP8 decoder */
-int rk3288_vpu_vp8d_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_vp8d_exit(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_vp8d_run(struct rk3288_vpu_ctx *ctx);
+/* Run ops for rk3288 VP8 decoder */
+int rk3288_vpu_vp8d_init(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_vp8d_exit(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_vp8d_run(struct rockchip_vpu_ctx *ctx);
-/* Run ops for VP8 encoder */
-int rk3288_vpu_vp8e_init(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_vp8e_exit(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_vp8e_run(struct rk3288_vpu_ctx *ctx);
-void rk3288_vpu_vp8e_done(struct rk3288_vpu_ctx *ctx,
+/* Run ops for rk3288 VP8 encoder */
+int rk3288_vpu_vp8e_init(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
enum vb2_buffer_state result);
-const struct rk3288_vp8e_reg_params *rk3288_vpu_vp8e_get_dummy_params(void);
+const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void);
-void rk3288_vpu_vp8e_assemble_bitstream(struct rk3288_vpu_ctx *ctx,
- struct rk3288_vpu_buf *dst_buf);
+void rk3288_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
+ struct rockchip_vpu_buf *dst_buf);
#endif /* ROCKCHIP_VPU_HW_H_ */
projects / firefly-linux-kernel-4.4.55.git / commitdiff