phy: phy-rockchip-typec: select phy select bit before TCPHY enter A2.

Set phy select bit in typec driver instead of setting it in dp driver,
which is used to fix dp phy power on failed error if only use typec1
as dp output.

Change-Id: I3949305724f5b3c12dc2f0ffefcbe4abf26d43dd
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>

diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c
index 26274654cf264b7e1e267880723c966cd02a1be8..2bad8008ad3e9860321c3ca9f34c9aad6b9ef224 100644 (file)
--- a/drivers/phy/phy-rockchip-typec.c
+++ b/drivers/phy/phy-rockchip-typec.c
@@ -269,6 +269,7 @@ struct rockchip_usb3phy_port_cfg {
        struct usb3phy_reg usb3host_port;
        struct usb3phy_reg external_psm;
        struct usb3phy_reg pipe_status;
+       struct usb3phy_reg uphy_dp_sel;
 };
 
 struct rockchip_typec_phy {
@@ -762,6 +763,7 @@ static const struct phy_ops rockchip_usb3_phy_ops = {
 static int rockchip_dp_phy_power_on(struct phy *phy)
 {
        struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
+       struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
        int new_mode, ret = 0;
        u32 val;
 
@@ -792,6 +794,8 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
                tcphy_phy_init(tcphy, new_mode);
        }
 
+       property_enable(tcphy, &cfg->uphy_dp_sel, 1);
+
        ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
                                 val, val & DP_MODE_A2, 1000,
                                 PHY_MODE_SET_TIMEOUT);
@@ -905,6 +909,11 @@ static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
        if (ret)
                return ret;
 
+       ret = tcphy_get_param(dev, &cfg->uphy_dp_sel,
+                             "rockchip,uphy-dp-sel");
+       if (ret)
+               return ret;
+
        tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node,
                                                          "rockchip,grf");
        if (IS_ERR(tcphy->grf_regs)) {