[SystemZ] Add ARK, AGRK, SRK and SGRK

The testsuite changes follow the same lines as for r186683.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 5ae6af23aec6fd0255fdd32fb69fb35cbcf7bba4..fe2b5367fc2b0e0cd03aad4f56977e23bdc83b0e 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -535,8 +535,8 @@ def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
 let Defs = [CC] in {
   // Addition of a register.
   let isCommutable = 1 in {
-    def AR  : BinaryRR <"a",  0x1A,   add, GR32, GR32>;
-    def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>;
+    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
+    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
   }
   def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
 
@@ -599,9 +599,9 @@ let Defs = [CC], Uses = [CC] in {
 // add-immediate instruction instead.
 let Defs = [CC] in {
   // Subtraction of a register.
-  def SR   : BinaryRR <"s",   0x1B,   sub,       GR32, GR32>;
+  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
   def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
-  def SGR  : BinaryRRE<"sg",  0xB909, sub,       GR64, GR64>;
+  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
 
   // Subtraction of memory.
   defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;

diff --git a/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index 04813f9d8bcd86c9ce1f5fa8050de6ad973751c0..6a919a724a5827b14488a27e8f100f8be1f1c968 100644 (file)
--- a/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -1,6 +1,6 @@
 ; Test 32-bit atomic additions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check addition of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {

diff --git a/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index f3814f20abe6327a281441cf2e7f6b3fe0460bd1..3b5c0d0b95fb8b972ed45134fc6464ed8b9dc0ae 100644 (file)
--- a/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -1,6 +1,6 @@
 ; Test 64-bit atomic additions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check addition of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {

diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index b0c17699572ab53bb2f1556fcd6314397bf6172a..64ec603fae8e75586dc6b4dd7b9eb8a5c6efb35f 100644 (file)
--- a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -1,6 +1,6 @@
 ; Test 32-bit atomic subtractions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check subtraction of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {

diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index c0fd9f9938dcf9cef05928b4dff9a65bff1236b0..18929b8c49d05c5bd1701e5efe3128328259f5f7 100644 (file)
--- a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -1,6 +1,6 @@
 ; Test 64-bit atomic subtractions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check subtraction of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {

diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll
index 0d4c8ce7a02a043bb0b615df274331403b3731c7..4386b5a4d496e1dad84a92e7bdc30c16cdcd1aff 100644 (file)
--- a/test/CodeGen/SystemZ/int-add-02.ll
+++ b/test/CodeGen/SystemZ/int-add-02.ll
@@ -1,6 +1,7 @@
 ; Test 32-bit addition in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 declare i32 @foo()
 

diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll
index 4f39a2d4dec49f23ed0209b1df20bc385fe4ef11..a05fdd9059c1063401f4877384e3129b4f0ce77c 100644 (file)
--- a/test/CodeGen/SystemZ/int-add-05.ll
+++ b/test/CodeGen/SystemZ/int-add-05.ll
@@ -1,6 +1,7 @@
 ; Test 64-bit addition in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 declare i64 @foo()
 

diff --git a/test/CodeGen/SystemZ/int-add-13.ll b/test/CodeGen/SystemZ/int-add-13.ll
new file mode 100644 (file)
index 0000000..7dfabbc
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-13.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of addition.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check ARK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ark %r2, %r3, %r4
+; CHECK: br %r14
+  %add = add i32 %b, %c
+  ret i32 %add
+}
+
+; Check that we can still use AR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: ar %r2, %r3
+; CHECK: br %r14
+  %add = add i32 %a, %b
+  ret i32 %add
+}
+
+; Check AGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: agrk %r2, %r3, %r4
+; CHECK: br %r14
+  %add = add i64 %b, %c
+  ret i64 %add
+}
+
+; Check that we can still use AGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: agr %r2, %r3
+; CHECK: br %r14
+  %add = add i64 %a, %b
+  ret i64 %add
+}

diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll
index ac3a5ff68b9a9bf2ee3687453f6cef14abe9122e..8d1e56ddcabab18586a5f6a59dda364587c1e48c 100644 (file)
--- a/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/test/CodeGen/SystemZ/int-sub-01.ll
@@ -1,6 +1,7 @@
 ; Test 32-bit subtraction.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 declare i32 @foo()
 

diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll
index 954775612b12a556afd49bf06ace94b96bdbff5c..85104536c5d74f80a8760c3da562f8420403d8c0 100644 (file)
--- a/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/test/CodeGen/SystemZ/int-sub-04.ll
@@ -1,6 +1,7 @@
 ; Test 64-bit subtraction in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 declare i64 @foo()
 

diff --git a/test/CodeGen/SystemZ/int-sub-08.ll b/test/CodeGen/SystemZ/int-sub-08.ll
new file mode 100644 (file)
index 0000000..f0a5e1e
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-sub-08.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of subtraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check SRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: srk %r2, %r3, %r4
+; CHECK: br %r14
+  %sub = sub i32 %b, %c
+  ret i32 %sub
+}
+
+; Check that we can still use SR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: sr %r2, %r3
+; CHECK: br %r14
+  %sub = sub i32 %a, %b
+  ret i32 %sub
+}
+
+; Check SGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: sgrk %r2, %r3, %r4
+; CHECK: br %r14
+  %sub = sub i64 %b, %c
+  ret i64 %sub
+}
+
+; Check that we can still use SGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: sgr %r2, %r3
+; CHECK: br %r14
+  %sub = sub i64 %a, %b
+  ret i64 %sub
+}

diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index 4352ae0fbf1f25f1513d2f2012989dac307db7ae..4c0755ae701115a268f6c36c8f4368d73792cb79 100644 (file)
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -175,6 +175,12 @@
 # CHECK: agr %r7, %r8
 0xb9 0x08 0x00 0x78
 
+# CHECK: agrk %r0, %r0, %r0
+0xb9 0xe8 0x00 0x00
+
+# CHECK: agrk %r2, %r3, %r4
+0xb9 0xe8 0x40 0x23
+
 # CHECK: agsi -524288, 0
 0xeb 0x00 0x00 0x00 0x80 0x7a
 
@@ -574,6 +580,12 @@
 # CHECK: ar %r7, %r8
 0x1a 0x78
 
+# CHECK: ark %r0, %r0, %r0
+0xb9 0xf8 0x00 0x00
+
+# CHECK: ark %r2, %r3, %r4
+0xb9 0xf8 0x40 0x23
+
 # CHECK: asi -524288, 0
 0xeb 0x00 0x00 0x00 0x80 0x6a
 
@@ -4936,6 +4948,12 @@
 # CHECK: sgr %r7, %r8
 0xb9 0x09 0x00 0x78
 
+# CHECK: sgrk %r0, %r0, %r0
+0xb9 0xe9 0x00 0x00
+
+# CHECK: sgrk %r2, %r3, %r4
+0xb9 0xe9 0x40 0x23
+
 # CHECK: sg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x09
 
@@ -5644,6 +5662,12 @@
 # CHECK: sr %r7, %r8
 0x1b 0x78
 
+# CHECK: srk %r0, %r0, %r0
+0xb9 0xf9 0x00 0x00
+
+# CHECK: srk %r2, %r3, %r4
+0xb9 0xf9 0x40 0x23
+
 # CHECK: stc %r0, 0
 0x42 0x00 0x00 0x00
 

diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s
index 6d1b086ad2d23c621196abf8660584395c03cf64..038f745a027693a6948d0f8c4736061900dd6378 100644 (file)
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@@ -69,6 +69,11 @@
        aghi    %r0, 32768
        aghi    %r0, foo
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: agrk   %r2,%r3,%r4
+
+       agrk    %r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: agsi   -524289, 0
 #CHECK: error: invalid operand
@@ -177,6 +182,11 @@
        aly     %r0, -524289
        aly     %r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ark    %r2,%r3,%r4
+
+       ark     %r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: asi    -524289, 0
 #CHECK: error: invalid operand
@@ -2264,6 +2274,11 @@
        sgf     %r0, -524289
        sgf     %r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: sgrk   %r2,%r3,%r4
+
+       sgrk    %r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: sh     %r0, -1
 #CHECK: error: invalid operand
@@ -2434,6 +2449,11 @@
 
        srak    %r2,%r3,4(%r5)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: srk    %r2,%r3,%r4
+
+       srk     %r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: srl    %r0,-1
 #CHECK: error: invalid operand

diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
index e00f9049f751b17d853941f037e53d587b9f8c7a..6e3a6a0ea0196947f7b2bfa2a0a6000b101e3563 100644 (file)
--- a/test/MC/SystemZ/insn-good-z196.s
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -1,6 +1,30 @@
 # For z196 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
 
+#CHECK: agrk   %r0, %r0, %r0           # encoding: [0xb9,0xe8,0x00,0x00]
+#CHECK: agrk   %r0, %r0, %r15          # encoding: [0xb9,0xe8,0xf0,0x00]
+#CHECK: agrk   %r0, %r15, %r0          # encoding: [0xb9,0xe8,0x00,0x0f]
+#CHECK: agrk   %r15, %r0, %r0          # encoding: [0xb9,0xe8,0x00,0xf0]
+#CHECK: agrk   %r7, %r8, %r9           # encoding: [0xb9,0xe8,0x90,0x78]
+
+       agrk    %r0,%r0,%r0
+       agrk    %r0,%r0,%r15
+       agrk    %r0,%r15,%r0
+       agrk    %r15,%r0,%r0
+       agrk    %r7,%r8,%r9
+
+#CHECK: ark    %r0, %r0, %r0           # encoding: [0xb9,0xf8,0x00,0x00]
+#CHECK: ark    %r0, %r0, %r15          # encoding: [0xb9,0xf8,0xf0,0x00]
+#CHECK: ark    %r0, %r15, %r0          # encoding: [0xb9,0xf8,0x00,0x0f]
+#CHECK: ark    %r15, %r0, %r0          # encoding: [0xb9,0xf8,0x00,0xf0]
+#CHECK: ark    %r7, %r8, %r9           # encoding: [0xb9,0xf8,0x90,0x78]
+
+       ark     %r0,%r0,%r0
+       ark     %r0,%r0,%r15
+       ark     %r0,%r15,%r0
+       ark     %r15,%r0,%r0
+       ark     %r7,%r8,%r9
+
 #CHECK: ngrk   %r0, %r0, %r0           # encoding: [0xb9,0xe4,0x00,0x00]
 #CHECK: ngrk   %r0, %r0, %r15          # encoding: [0xb9,0xe4,0xf0,0x00]
 #CHECK: ngrk   %r0, %r15, %r0          # encoding: [0xb9,0xe4,0x00,0x0f]
@@ -49,6 +73,18 @@
        ork     %r15,%r0,%r0
        ork     %r7,%r8,%r9
 
+#CHECK: sgrk   %r0, %r0, %r0           # encoding: [0xb9,0xe9,0x00,0x00]
+#CHECK: sgrk   %r0, %r0, %r15          # encoding: [0xb9,0xe9,0xf0,0x00]
+#CHECK: sgrk   %r0, %r15, %r0          # encoding: [0xb9,0xe9,0x00,0x0f]
+#CHECK: sgrk   %r15, %r0, %r0          # encoding: [0xb9,0xe9,0x00,0xf0]
+#CHECK: sgrk   %r7, %r8, %r9           # encoding: [0xb9,0xe9,0x90,0x78]
+
+       sgrk    %r0,%r0,%r0
+       sgrk    %r0,%r0,%r15
+       sgrk    %r0,%r15,%r0
+       sgrk    %r15,%r0,%r0
+       sgrk    %r7,%r8,%r9
+
 #CHECK: sllk   %r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
 #CHECK: sllk   %r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
 #CHECK: sllk   %r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
@@ -101,6 +137,18 @@
        srak    %r0,%r0,524287(%r1)
        srak    %r0,%r0,524287(%r15)
 
+#CHECK: srk    %r0, %r0, %r0           # encoding: [0xb9,0xf9,0x00,0x00]
+#CHECK: srk    %r0, %r0, %r15          # encoding: [0xb9,0xf9,0xf0,0x00]
+#CHECK: srk    %r0, %r15, %r0          # encoding: [0xb9,0xf9,0x00,0x0f]
+#CHECK: srk    %r15, %r0, %r0          # encoding: [0xb9,0xf9,0x00,0xf0]
+#CHECK: srk    %r7, %r8, %r9           # encoding: [0xb9,0xf9,0x90,0x78]
+
+       srk     %r0,%r0,%r0
+       srk     %r0,%r0,%r15
+       srk     %r0,%r15,%r0
+       srk     %r15,%r0,%r0
+       srk     %r7,%r8,%r9
+
 #CHECK: srlk   %r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0xde]
 #CHECK: srlk   %r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xde]
 #CHECK: srlk   %r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xde]