// Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty())
- OS << "NULL, ";
+ OS << "nullptr, ";
else
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty())
- OS << "NULL, ";
+ OS << "nullptr, ";
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
// Emit the operand info.
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
- OS << "0";
+ OS << "nullptr";
else
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
else if (!Inst.DeprecatedReason.empty())
// Emit the Subtarget feature.
OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
- << ",0";
+ << ",nullptr";
else
// Instruction isn't deprecated.
- OS << ",0,0";
+ OS << ",0,nullptr";
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
for (unsigned i = 0; i < NumSets; ++i ) {
OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
}
- OS << " 0 };\n"
+ OS << " nullptr };\n"
<< " return PressureNameTable[Idx];\n"
<< "}\n\n";
// Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) {
OS << "\nstatic const TargetRegisterClass *const "
- << "NullRegClasses[] = { NULL };\n\n";
+ << "NullRegClasses[] = { nullptr };\n\n";
// Emit register class bit mask tables. The first bit mask emitted for a
// register class, RC, is the set of sub-classes, including RC itself.
<< RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i)
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
- OS << " NULL\n};\n\n";
+ OS << " nullptr\n};\n\n";
}
// Emit methods.
else
OS << RC.getName() << "Superclasses,\n ";
if (RC.AltOrderSelect.empty())
- OS << "0\n";
+ OS << "nullptr\n";
else
OS << RC.getName() << "GetRawAllocationOrder\n";
OS << " };\n\n";
<< " if (!Idx) return RC;\n --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " unsigned TV = Table[RC->getID()][Idx];\n"
- << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
+ << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
}
EmitRegUnitPressure(OS, RegBank, ClassName);