Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 445fb26fc0062be1b33b6aa4201b14afd0d1128d..2f51144e473a890a1da402395fa53fe11a277180 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -101,31 +101,31 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
   let MethodBodies = [{
     // FP is R11, R9 is available.
     static const unsigned ARM_GPR_AO_1[] = {
-      ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+      ARM::R3, ARM::R2, ARM::R1, ARM::R0,
       ARM::R4, ARM::R5, ARM::R6, ARM::R7,
       ARM::R8, ARM::R9, ARM::R10,
       ARM::LR, ARM::R11 };
     // FP is R11, R9 is not available.
     static const unsigned ARM_GPR_AO_2[] = {
-      ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+      ARM::R3, ARM::R2, ARM::R1, ARM::R0,
       ARM::R4, ARM::R5, ARM::R6, ARM::R7,
       ARM::R8, ARM::R10,
       ARM::LR, ARM::R11 };
     // FP is R7, R9 is available.
     static const unsigned ARM_GPR_AO_3[] = {
-      ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+      ARM::R3, ARM::R2, ARM::R1, ARM::R0,
       ARM::R4, ARM::R5, ARM::R6, ARM::R8,
       ARM::R9, ARM::R10,ARM::R11,
       ARM::LR, ARM::R7 };
     // FP is R7, R9 is not available.
     static const unsigned ARM_GPR_AO_4[] = {
-      ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+      ARM::R3, ARM::R2, ARM::R1, ARM::R0,
       ARM::R4, ARM::R5, ARM::R6, ARM::R8,
       ARM::R10,ARM::R11,
       ARM::LR, ARM::R7 };
     // FP is R7, only low registers available.
     static const unsigned THUMB_GPR_AO[] = {
-      ARM::R0, ARM::R1, ARM::R2,
+      ARM::R2, ARM::R1, ARM::R0,
       ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
 
     GPRClass::iterator