#address-cells = <1>;
#size-cells = <1>;
- i2s0_pll_div: i2s0_pll_div {
+ i2s_pll_div: i2s_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_i2s_pll>;
/* reg[7]: reserved */
- clk_i2s0: i2s0_mux {
+ clk_i2s: i2s_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
- clocks = <&clk_i2s_pll>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
- clock-output-names = "clk_i2s0";
+ clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
+ clock-output-names = "clk_i2s";
#clock-cells = <0>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
- clk_i2s0_out: i2s0_outclk_mux {
+ clk_i2s_out: i2s_outclk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <12 1>;
- clocks = <&clk_i2s0>, <&xin12m>;
- clock-output-names = "clk_i2s0_out";
+ clocks = <&clk_i2s>, <&xin12m>;
+ clock-output-names = "clk_i2s_out";
#clock-cells = <0>;
};
#address-cells = <1>;
#size-cells = <1>;
- i2s0_frac: i2s0_frac {
+ i2s_frac: i2s_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_i2s_pll>;
- clock-output-names = "i2s0_frac";
+ clock-output-names = "i2s_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
#address-cells = <1>;
#size-cells = <1>;
- clk_sdmmc0_div: clk_sdmmc0_div {
+ clk_sdmmc_div: clk_sdmmc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
- clocks = <&clk_sdmmc0>;
- clock-output-names = "clk_sdmmc0";
+ clocks = <&clk_sdmmc>;
+ clock-output-names = "clk_sdmmc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
- clk_sdmmc0: clk_sdmmc0_mux {
+ clk_sdmmc: clk_sdmmc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
- clock-output-names = "clk_sdmmc0";
+ clock-output-names = "clk_sdmmc";
#clock-cells = <0>;
};
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
- <&clk_i2s0_out>, <&clk_i2s_pll>,
- <&i2s0_frac>, <&clk_i2s0>,
+ <&clk_i2s_out>, <&clk_i2s_pll>,
+ <&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
- "clk_i2s0_out", "clk_i2s_pll",
- "i2s0_frac", "g_clk_i2s0",
+ "clk_i2s_out", "clk_i2s_pll",
+ "i2s_frac", "g_clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
- "reserved", "g_pclk_uart2",
+ "reserved", "g_pclk_uart3",
- "g_pclk_uart3", "g_pclk_i2c2",
+ "g_pclk_uart4", "g_pclk_i2c2",
"g_pclk_i2c3", "g_pclk_i2c4";
#clock-cells = <1>;
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
- <&clk_sdmmc0>, <&clk_sdio0>,
+ <&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
- "clk_sdmmc0", "clk_sdio0",
+ "clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
//pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
/*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_3 --clk_emmc_src_gate_en*/
- //clocks = <&clk_gates8 0>, <&clk_gates8 0>;
- clock-names = "emmc_clk", "arbi_emmc_clk";
+ clocks = <&clk_emmc>, <&clk_gates8 6>;
+ clock-names = "clk_mmc", "hclk_mmc";
num-slots = <1>;
fifo-depth = <0x80>;
bus-width = <4>;
//pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
/*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_0 --clk_mmc0_src_gate_en*/
- //clocks = <&clk_gates8 0>, <&clk_gates13 0>;
- clock-names = "sdmmc_clk", "arbi_sdmmc_clk";
+ clocks = <&clk_sdmmc>, <&clk_gates8 3>;
+ clock-names = "clk_mmc", "hclk_mmc";
num-slots = <1>;
fifo-depth = <0x100>;
bus-width = <4>;
//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
/*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_1 --clk_sdio0_src_gate_en*/
- //clocks = <&clk_gates8 0>, <&clk_gates13 1>;
- clock-names = "sdio_clk", "arbi_sdio_clk";
+ clocks = <&clk_sdio0>, <&clk_gates8 4>;
+ clock-names = "clk_mmc", "hclk_mmc";
num-slots = <1>;
fifo-depth = <0x100>;
//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
/*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
- //clocks = <&clk_gates8 0>, <&clk_gates13 2>;
- clock-names = "sdio1_clk", "arbi_sdio1_clk";
+ clocks = <&clk_sdio1>, <&clk_gates8 5>;
+ clock-names = "clk_mmc", "hclk_mmc";
num-slots = <1>;
fifo-depth = <0x100>;
reg = <0xff180000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
- //clocks = <&clk_uart0>, <&clk_gates8 0>;
- //clock-names = "sclk_uart", "pclk_uart";
+ clocks = <&clk_uart0>, <&clk_gates6 8>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&pdma1 1>, <&pdma1 2>;
reg = <0xff190000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
- //clocks = <&clk_uart1>, <&clk_gates8 1>;
- //clock-names = "sclk_uart", "pclk_uart";
+ clocks = <&clk_uart1>, <&clk_gates6 9>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&pdma1 3>, <&pdma1 4>;
reg = <0xff690000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
+ clocks = <&clk_uart2>, <&clk_gates11 9>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&pdma0 4>, <&pdma0 5>;
reg = <0xff1b0000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
- //clocks = <&clk_uart2>, <&clk_gates8 2>;
- //clock-names = "sclk_uart", "pclk_uart";
+ clocks = <&clk_uart3>, <&clk_gates6 11>;
+ clock-names = "sclk_uart", "pclk_uart";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
reg = <0xff1c0000 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
- //clocks = <&clk_uart3>, <&clk_gates8 3>;
- //clock-names = "sclk_uart", "pclk_uart";
+ clocks = <&clk_uart4>, <&clk_gates6 12>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&pdma1 9>, <&pdma1 10>;
pinctrl-0 = <&i2c0_sda &i2c0_scl>;
pinctrl-1 = <&i2c0_gpio>;
gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 4>;
+ clocks = <&clk_gates10 2>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c1_sda &i2c1_scl>;
pinctrl-1 = <&i2c1_gpio>;
gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 5>;
+ clocks = <&clk_gates10 3>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c2_sda &i2c2_scl>;
pinctrl-1 = <&i2c2_gpio>;
gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 6>;
+ clocks = <&clk_gates6 13>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c3_sda &i2c3_scl>;
pinctrl-1 = <&i2c3_gpio>;
gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 7>;
+ clocks = <&clk_gates6 14>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c4_sda &i2c4_scl>;
pinctrl-1 = <&i2c4_gpio>;
gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 8>;
+ clocks = <&clk_gates6 15>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c5_sda &i2c5_scl>;
pinctrl-1 = <&i2c5_gpio>;
gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
- //clocks = <&clk_gates8 8>;
+ clocks = <&clk_gates7 0>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
- clocks = <&aclk_vio1>, <&dclk_lcdc1>, <&hclk_vio>;
+ clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
};
//pinctrl-0 = <&lcdc0_lcdc>;
//pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
- clocks = <&aclk_vio0>, <&dclk_lcdc0>, <&hclk_vio>;
+ clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
};
io-channel-ranges;
rockchip,adc-vref = <1800>;
clock-frequency = <1000000>;
+ clocks = <&clk_saradc>, <&clk_gates7 1>;
clock-names = "saradc", "pclk_saradc";
status = "disabled";
};
compatible = "rockchip-spdif";
reg = <0xff8b0000 0x10000>; //8channel
//reg = <ff880000 0x10000>;//2channel
- clocks = <&clk_spdif>;
- clock-names = "spdif_mclk";
+ clocks = <&clk_spdif>, <&clk_spdif_8ch>;
+ clock-names = "spdif_mclk","spdif_8ch_mclk";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 3>;
//dmas = <&pdma0 2>; //2channel
reg = <0xff9a0000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
-
+ clocks = <&clk_vepu>, <&hclk_vepu>;
clock-names = "aclk_vcodec", "hclk_vcodec";
name = "vpu_service";
status = "disabled";
reg = <0xff9c0000 0x800>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
-
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
+ clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
+ clock-names = "aclk_hevc", "hclk_hevc", "clk_core", "clk_cabac";
name = "hevc_service";
status = "disabled";
};
compatible = "rockchip,iep";
reg = <0xff900000 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-
+ clocks = <&clk_gates15 2>, <&clk_gates15 3>;
clock_names = "aclk_iep", "hclk_iep";
status = "disabled";
};
projects / firefly-linux-kernel-4.4.55.git / commitdiff