projects
/
oota-llvm.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
fe27c51
)
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
author
Bob Wilson
<bob.wilson@apple.com>
Wed, 7 Oct 2009 23:54:04 +0000
(23:54 +0000)
committer
Bob Wilson
<bob.wilson@apple.com>
Wed, 7 Oct 2009 23:54:04 +0000
(23:54 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMISelDAGToDAG.cpp
patch
|
blob
|
history
lib/Target/ARM/ARMInstrNEON.td
patch
|
blob
|
history
lib/Target/ARM/NEONPreAllocPass.cpp
patch
|
blob
|
history
test/CodeGen/ARM/vld4.ll
patch
|
blob
|
history
diff --git
a/lib/Target/ARM/ARMISelDAGToDAG.cpp
b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index c68c645c2cb15683d89426d079d4b55752f3e04a..efa6e48b0558fe50d9d9249a8dedcea054787099 100644
(file)
--- a/
lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/
lib/Target/ARM/ARMISelDAGToDAG.cpp
@@
-1454,6
+1454,7
@@
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD4d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD4d32; break;
case MVT::v4i16: Opc = ARM::VLD4d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD4d32; break;
+ case MVT::v1i64: Opc = ARM::VLD4d64; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
diff --git
a/lib/Target/ARM/ARMInstrNEON.td
b/lib/Target/ARM/ARMInstrNEON.td
index e7601b2346ae818e6119311fc5c9297907b62c92..d3aeeed192bd71e94c76661e86906df4ca879e0b 100644
(file)
--- a/
lib/Target/ARM/ARMInstrNEON.td
+++ b/
lib/Target/ARM/ARMInstrNEON.td
@@
-247,6
+247,10
@@
class VLD4WB<bits<4> op7_4, string OpcodeStr>
def VLD4d8 : VLD4D<0b0000, "vld4.8">;
def VLD4d16 : VLD4D<0b0100, "vld4.16">;
def VLD4d32 : VLD4D<0b1000, "vld4.32">;
def VLD4d8 : VLD4D<0b0000, "vld4.8">;
def VLD4d16 : VLD4D<0b0100, "vld4.16">;
def VLD4d32 : VLD4D<0b1000, "vld4.32">;
+def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
+ (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
+ (ins addrmode6:$addr), IIC_VLD1,
+ "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>;
// vld4 to double-spaced even registers.
def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
// vld4 to double-spaced even registers.
def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
diff --git
a/lib/Target/ARM/NEONPreAllocPass.cpp
b/lib/Target/ARM/NEONPreAllocPass.cpp
index 52a43aaccfddc016bf7a1cf2803cf8929bee4a8c..5de2810f33d96b763ca1c7a303b5944916010c7b 100644
(file)
--- a/
lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/
lib/Target/ARM/NEONPreAllocPass.cpp
@@
-96,6
+96,7
@@
static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:
+ case ARM::VLD4d64:
case ARM::VLD4LNd8:
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
case ARM::VLD4LNd8:
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
diff --git
a/test/CodeGen/ARM/vld4.ll
b/test/CodeGen/ARM/vld4.ll
index 08f67a793a56867cee7a722b2ce58d67358fcfff..0624f2977ea46280729be08e3afb63dbf691ea53 100644
(file)
--- a/
test/CodeGen/ARM/vld4.ll
+++ b/
test/CodeGen/ARM/vld4.ll
@@
-4,6
+4,7
@@
%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
+%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
@@
-50,6
+51,16
@@
define <2 x float> @vld4f(float* %A) nounwind {
ret <2 x float> %tmp4
}
ret <2 x float> %tmp4
}
+define <1 x i64> @vld4i64(i64* %A) nounwind {
+;CHECK: vld4i64:
+;CHECK: vld1.64
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i64* %A)
+ %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
+}
+
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
;CHECK: vld4Qi8:
;CHECK: vld4.8
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
;CHECK: vld4Qi8:
;CHECK: vld4.8
@@
-98,6
+109,7
@@
declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*) nounwind readonl
declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*) nounwind readonly
declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*) nounwind readonly
declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*) nounwind readonly
declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*) nounwind readonly
declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*) nounwind readonly
declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*) nounwind readonly
+declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8*) nounwind readonly
declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*) nounwind readonly
declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*) nounwind readonly
declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*) nounwind readonly
declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*) nounwind readonly