// acceptable range for this architecture.
//
//
- if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
+ if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
std::cerr << "llvm.writeport: Address size is not 16 bits\n";
exit (1);
}
// Now, move the I/O port address into the DX register and the value to
// write into the AL/AX/EAX register.
//
- BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
- switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
+ switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
case 1:
- BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT8, 0);
break;
case 2:
- BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT16, 0);
break;
case 4:
- BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT32, 0);
break;
default:
// acceptable range for this architecture.
//
//
- if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
+ if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {
std::cerr << "llvm.writeport: Address size is not 16 bits\n";
exit (1);
}
// Now, move the I/O port address into the DX register and the value to
// write into the AL/AX/EAX register.
//
- BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
- switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
+ switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {
case 1:
- BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT8, 0);
break;
case 2:
- BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT16, 0);
break;
case 4:
- BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
+ BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));
BuildMI(BB, X86::OUT32, 0);
break;
default:
case Intrinsic::writeport:
Assert1(FT->getNumParams() == 2,
"Illegal # arguments for intrinsic function!", IF);
- Assert1(FT->getParamType(0)->isUnsigned(),
+ Assert1(FT->getParamType(0)->isIntegral(),
"First argument not unsigned int!", IF);
- Assert1(FT->getParamType(1)->isIntegral(),
+ Assert1(FT->getParamType(1)->isUnsigned(),
"First argument not unsigned int!", IF);
NumArgs = 2;
break;