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(parent: ca3cd41) | patch
Added the missing bit definition for the 4th bit of the STR (post reg) instruction...
authorSilviu Baranga <silviu.baranga@arm.com>
Fri, 11 May 2012 09:28:27 +0000 (09:28 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Fri, 11 May 2012 09:28:27 +0000 (09:28 +0000)
commit169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23
tree408238e8f54232584a1ded72f584fd51d0fb95c7tree | snapshot
parentca3cd419a52c1dedee133d79772ef97f30e5d20bcommit | diff
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrFormats.td diff | blob | history
lib/Target/ARM/ARMInstrInfo.td diff | blob | history
test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt [new file with mode: 0644] blob
test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors