[lib/Fuzzer] detach the pulse thread instad of joining it

[oota-llvm.git] / utils / TableGen / X86RecognizableInstr.h

diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index 70c785ed8896d6f8a8618b733df7c4b7298995ef..28e10535508d70e7eb006e48fbae09034836d4c6 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -14,8 +14,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef X86RECOGNIZABLEINSTR_H
-#define X86RECOGNIZABLEINSTR_H
+#ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
+#define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
 
 #include "CodeGenTarget.h"
 #include "X86DisassemblerTables.h"
@@ -50,8 +50,8 @@ private:
   uint8_t Encoding;
   /// The OpSize field from the record
   uint8_t OpSize;
-  /// The hasAdSizePrefix field from the record
-  bool HasAdSizePrefix;
+  /// The AdSize field from the record
+  uint8_t AdSize;
   /// The hasREX_WPrefix field from the record
   bool HasREX_WPrefix;
   /// The hasVEX_4V field from the record
@@ -74,14 +74,12 @@ private:
   bool HasEVEX_KZ;
   /// The hasEVEX_B field from the record
   bool HasEVEX_B;
-  /// The hasLockPrefix field from the record
-  bool HasLockPrefix;
-  /// The hasREPPrefix field from the record
-  bool HasREPPrefix;
   /// The isCodeGenOnly field from the record
   bool IsCodeGenOnly;
   /// The ForceDisassemble field from the record
   bool ForceDisassemble;
+  // The CD8_Scale field from the record
+  uint8_t CD8_Scale;
   // Whether the instruction has the predicate "In64BitMode"
   bool Is64Bit;
   // Whether the instruction has the predicate "In32BitMode"
@@ -110,28 +108,6 @@ private:
   ///
   /// @return - The context in which the instruction is valid.
   InstructionContext insnContext() const;
-  
-  enum filter_ret {
-    FILTER_STRONG,    // instruction has no place in the instruction tables
-    FILTER_WEAK,      // instruction may conflict, and should be eliminated if
-                      // it does
-    FILTER_NORMAL     // instruction should have high priority and generate an
-                      // error if it conflcits with any other FILTER_NORMAL
-                      // instruction
-  };
-      
-  /// filter - Determines whether the instruction should be decodable.  Some 
-  ///   instructions are pure intrinsics and use unencodable operands; many
-  ///   synthetic instructions are duplicates of other instructions; other
-  ///   instructions only differ in the logical way in which they are used, and
-  ///   have the same decoding.  Because these would cause decode conflicts,
-  ///   they must be filtered out.
-  ///
-  /// @return - The degree of filtering to be applied (see filter_ret).
-  filter_ret filter() const;
-
-  /// hasFROperands - Returns true if any operand is a FR operand.
-  bool hasFROperands() const;
 
   /// typeFromString - Translates an operand type from the string provided in
   ///   the LLVM tables to an OperandType for use in the operand specifier.
@@ -179,6 +155,9 @@ private:
   static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
                                                              uint8_t OpSize);
 
+  /// \brief Adjust the encoding type for an operand based on the instruction.
+  void adjustOperandEncoding(OperandEncoding &encoding);
+
   /// handleOperand - Converts a single operand from the LLVM table format to
   ///   the emitted table format, handling any duplicate operands it encounters
   ///   and then one non-duplicate.