Remove unnecessary stirng comparison from disassembler.

[oota-llvm.git] / utils / TableGen / X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 678e843e9c91a60e5bed8d1ce5afe3e9aa36cf82..6ae7c3820e4d1d9660a6f7a8616b328d5707df3b 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -277,7 +277,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   }
   // FIXME: These instructions aren't marked as 64-bit in any way
   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
-             Rec->getName() == "MASKMOVDQU64" ||
              Rec->getName() == "POPFS64" ||
              Rec->getName() == "POPGS64" ||
              Rec->getName() == "PUSHFS64" ||
@@ -300,7 +299,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
 
   RecognizableInstr recogInstr(tables, insn, uid);
 
-  recogInstr.emitInstructionSpecifier(tables);
+  recogInstr.emitInstructionSpecifier();
 
   if (recogInstr.shouldBeEmitted())
     recogInstr.emitDecodePath(tables);
@@ -503,10 +502,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
   // printed as a separate "instruction".
 
-  if (Name.find("_Int") != Name.npos       ||
-      Name.find("Int_") != Name.npos)
-    return FILTER_STRONG;
-
   // Filter out instructions with segment override prefixes.
   // They're too messy to handle now and we'll special case them if needed.
 
@@ -595,7 +590,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
   ++physicalOperandIndex;
 }
 
-void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
+void RecognizableInstr::emitInstructionSpecifier() {
   Spec->name       = Name;
 
   if (!ShouldBeEmitted)
@@ -1162,8 +1157,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
   assert(filter && "Filter not set");
 
   if (Form == X86Local::AddRegFrm) {
-    assert(opcodeToSet < 0xf9 &&
-           "Not enough room for all ADDREG_FRM operands");
+    assert(((opcodeToSet & 7) == 0) &&
+           "ADDREG_FRM opcode not aligned");
 
     uint8_t currentOpcode;
 
@@ -1175,18 +1170,12 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
                             currentOpcode,
                             *filter,
                             UID, Is32Bit, IgnoresVEX_L);
-
-    Spec->modifierType = MODIFIER_OPCODE;
-    Spec->modifierBase = opcodeToSet;
   } else {
     tables.setTableFields(opcodeType,
                           insnContext(),
                           opcodeToSet,
                           *filter,
                           UID, Is32Bit, IgnoresVEX_L);
-
-    Spec->modifierType = MODIFIER_NONE;
-    Spec->modifierBase = opcodeToSet;
   }
 
   delete filter;