Remove unnecessary stirng comparison from disassembler.

[oota-llvm.git] / utils / TableGen / X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 3472c8a046c0d6d8eb20c08aba66bd0ef44b1574..6ae7c3820e4d1d9660a6f7a8616b328d5707df3b 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -277,7 +277,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   }
   // FIXME: These instructions aren't marked as 64-bit in any way
   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
-             Rec->getName() == "MASKMOVDQU64" ||
              Rec->getName() == "POPFS64" ||
              Rec->getName() == "POPGS64" ||
              Rec->getName() == "PUSHFS64" ||
@@ -300,7 +299,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
 
   RecognizableInstr recogInstr(tables, insn, uid);
 
-  recogInstr.emitInstructionSpecifier(tables);
+  recogInstr.emitInstructionSpecifier();
 
   if (recogInstr.shouldBeEmitted())
     recogInstr.emitDecodePath(tables);
@@ -503,10 +502,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
   // printed as a separate "instruction".
 
-  if (Name.find("_Int") != Name.npos       ||
-      Name.find("Int_") != Name.npos)
-    return FILTER_STRONG;
-
   // Filter out instructions with segment override prefixes.
   // They're too messy to handle now and we'll special case them if needed.
 
@@ -595,7 +590,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
   ++physicalOperandIndex;
 }
 
-void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
+void RecognizableInstr::emitInstructionSpecifier() {
   Spec->name       = Name;
 
   if (!ShouldBeEmitted)
@@ -1075,14 +1070,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
   case X86Local::DE:
   case X86Local::DF:
     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
+    assert(Form == X86Local::RawFrm);
     opcodeType = ONEBYTE;
-    if (Form == X86Local::AddRegFrm) {
-      Spec->modifierType = MODIFIER_MODRM;
-      Spec->modifierBase = Opcode;
-      filter = new AddRegEscapeFilter(Opcode);
-    } else {
-      filter = new EscapeFilter(true, Opcode);
-    }
+    filter = new ExactFilter(Opcode);
     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
     break;
   case X86Local::REP:
@@ -1127,7 +1117,30 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
     case 0xdd:
     case 0xde:
     case 0xdf:
-      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
+      switch (Form) {
+      default:
+        llvm_unreachable("Unhandled escape opcode form");
+      case X86Local::MRM0r:
+      case X86Local::MRM1r:
+      case X86Local::MRM2r:
+      case X86Local::MRM3r:
+      case X86Local::MRM4r:
+      case X86Local::MRM5r:
+      case X86Local::MRM6r:
+      case X86Local::MRM7r:
+        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
+        break;
+      case X86Local::MRM0m:
+      case X86Local::MRM1m:
+      case X86Local::MRM2m:
+      case X86Local::MRM3m:
+      case X86Local::MRM4m:
+      case X86Local::MRM5m:
+      case X86Local::MRM6m:
+      case X86Local::MRM7m:
+        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
+        break;
+      } // switch (Form)
       break;
     default:
       if (needsModRMForDecode(Form))
@@ -1144,40 +1157,25 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
   assert(filter && "Filter not set");
 
   if (Form == X86Local::AddRegFrm) {
-    if(Spec->modifierType != MODIFIER_MODRM) {
-      assert(opcodeToSet < 0xf9 &&
-             "Not enough room for all ADDREG_FRM operands");
-
-      uint8_t currentOpcode;
-
-      for (currentOpcode = opcodeToSet;
-           currentOpcode < opcodeToSet + 8;
-           ++currentOpcode)
-        tables.setTableFields(opcodeType,
-                              insnContext(),
-                              currentOpcode,
-                              *filter,
-                              UID, Is32Bit, IgnoresVEX_L);
-
-      Spec->modifierType = MODIFIER_OPCODE;
-      Spec->modifierBase = opcodeToSet;
-    } else {
-      // modifierBase was set where MODIFIER_MODRM was set
+    assert(((opcodeToSet & 7) == 0) &&
+           "ADDREG_FRM opcode not aligned");
+
+    uint8_t currentOpcode;
+
+    for (currentOpcode = opcodeToSet;
+         currentOpcode < opcodeToSet + 8;
+         ++currentOpcode)
       tables.setTableFields(opcodeType,
                             insnContext(),
-                            opcodeToSet,
+                            currentOpcode,
                             *filter,
                             UID, Is32Bit, IgnoresVEX_L);
-    }
   } else {
     tables.setTableFields(opcodeType,
                           insnContext(),
                           opcodeToSet,
                           *filter,
                           UID, Is32Bit, IgnoresVEX_L);
-
-    Spec->modifierType = MODIFIER_NONE;
-    Spec->modifierBase = opcodeToSet;
   }
 
   delete filter;
@@ -1247,6 +1245,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
   TYPE("i32imm_pcrel",        TYPE_REL32)
   TYPE("SSECC",               TYPE_IMM3)
   TYPE("AVXCC",               TYPE_IMM5)
+  TYPE("AVX512RC",            TYPE_IMM32)
   TYPE("brtarget",            TYPE_RELv)
   TYPE("uncondbrtarget",      TYPE_RELv)
   TYPE("brtarget8",           TYPE_REL8)
@@ -1304,6 +1303,7 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString
   ENCODING("u32u8imm",        ENCODING_IB)
   ENCODING("SSECC",           ENCODING_IB)
   ENCODING("AVXCC",           ENCODING_IB)
+  ENCODING("AVX512RC",        ENCODING_IB)
   ENCODING("i16imm",          ENCODING_Iv)
   ENCODING("i16i8imm",        ENCODING_IB)
   ENCODING("i32imm",          ENCODING_Iv)
@@ -1328,6 +1328,7 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString
 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
   (const std::string &s,
    bool hasOpSizePrefix) {
+  ENCODING("RST",             ENCODING_FP)
   ENCODING("GR16",            ENCODING_RM)
   ENCODING("GR32",            ENCODING_RM)
   ENCODING("GR32orGR64",      ENCODING_RM)
@@ -1480,7 +1481,6 @@ OperandEncoding RecognizableInstr::relocationEncodingFromString
 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
   (const std::string &s,
    bool hasOpSizePrefix) {
-  ENCODING("RST",             ENCODING_I)
   ENCODING("GR32",            ENCODING_Rv)
   ENCODING("GR64",            ENCODING_RO)
   ENCODING("GR16",            ENCODING_Rv)