Prefix = byteFromRec(Rec, "Prefix");
Opcode = byteFromRec(Rec, "Opcode");
Form = byteFromRec(Rec, "FormBits");
- SegOvr = byteFromRec(Rec, "SegOvrBits");
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
+ ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
Name = Rec->getName();
AsmString = Rec->getValueAsString("AsmString");
IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
(Name.find("CRC32") != Name.npos);
- HasFROperands = hasFROperands();
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
break;
}
}
- // FIXME: These instructions aren't marked as 64-bit in any way
- Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
- Rec->getName() == "MASKMOVDQU64" ||
- Rec->getName() == "POPFS64" ||
- Rec->getName() == "POPGS64" ||
- Rec->getName() == "PUSHFS64" ||
- Rec->getName() == "PUSHGS64" ||
- Rec->getName() == "REX64_PREFIX" ||
- Rec->getName().find("MOV64") != Name.npos ||
- Rec->getName().find("PUSH64") != Name.npos ||
- Rec->getName().find("POP64") != Name.npos;
ShouldBeEmitted = true;
}
RecognizableInstr recogInstr(tables, insn, uid);
- recogInstr.emitInstructionSpecifier(tables);
+ recogInstr.emitInstructionSpecifier();
if (recogInstr.shouldBeEmitted())
recogInstr.emitDecodePath(tables);
assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
- if (Form == X86Local::Pseudo ||
- (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
- Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
+ if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
return FILTER_STRONG;
// Filter out artificial instructions but leave in the LOCK_PREFIX so it is
// printed as a separate "instruction".
- if (Name.find("_Int") != Name.npos ||
- Name.find("Int_") != Name.npos)
- return FILTER_STRONG;
-
- // Filter out instructions with segment override prefixes.
- // They're too messy to handle now and we'll special case them if needed.
-
- if (SegOvr)
- return FILTER_STRONG;
-
/////////////////
// FILTER_WEAK
if (HasLockPrefix)
return FILTER_WEAK;
- // Filter out alternate forms of AVX instructions
- if (Name.find("_alt") != Name.npos ||
- (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
- Name.find("_64mr") != Name.npos ||
- Name.find("rr64") != Name.npos)
- return FILTER_WEAK;
-
// Special cases.
- if (Name == "PUSH64i16" ||
- Name == "MOVPQI2QImr" ||
- Name == "VMOVPQI2QImr" ||
- Name == "VMASKMOVDQU64")
+ if (Name == "VMASKMOVDQU64")
return FILTER_WEAK;
// XACQUIRE and XRELEASE reuse REPNE and REP respectively.
return FILTER_NORMAL;
}
-bool RecognizableInstr::hasFROperands() const {
- const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
- unsigned numOperands = OperandList.size();
-
- for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
- const std::string &recName = OperandList[operandIndex].Rec->getName();
-
- if (recName.find("FR") != recName.npos)
- return true;
- }
- return false;
-}
-
void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
unsigned &physicalOperandIndex,
unsigned &numPhysicalOperands,
++physicalOperandIndex;
}
-void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
+void RecognizableInstr::emitInstructionSpecifier() {
Spec->name = Name;
if (!ShouldBeEmitted)
assert(filter && "Filter not set");
if (Form == X86Local::AddRegFrm) {
- assert(opcodeToSet < 0xf9 &&
- "Not enough room for all ADDREG_FRM operands");
+ assert(((opcodeToSet & 7) == 0) &&
+ "ADDREG_FRM opcode not aligned");
uint8_t currentOpcode;
currentOpcode,
*filter,
UID, Is32Bit, IgnoresVEX_L);
-
- Spec->modifierType = MODIFIER_OPCODE;
- Spec->modifierBase = opcodeToSet;
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
UID, Is32Bit, IgnoresVEX_L);
-
- Spec->modifierType = MODIFIER_NONE;
- Spec->modifierBase = opcodeToSet;
}
delete filter;
TYPE("i32imm_pcrel", TYPE_REL32)
TYPE("SSECC", TYPE_IMM3)
TYPE("AVXCC", TYPE_IMM5)
+ TYPE("AVX512RC", TYPE_IMM32)
TYPE("brtarget", TYPE_RELv)
TYPE("uncondbrtarget", TYPE_RELv)
TYPE("brtarget8", TYPE_REL8)
ENCODING("u32u8imm", ENCODING_IB)
ENCODING("SSECC", ENCODING_IB)
ENCODING("AVXCC", ENCODING_IB)
+ ENCODING("AVX512RC", ENCODING_IB)
ENCODING("i16imm", ENCODING_Iv)
ENCODING("i16i8imm", ENCODING_IB)
ENCODING("i32imm", ENCODING_Iv)
OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
(const std::string &s,
bool hasOpSizePrefix) {
- ENCODING("RST", ENCODING_I)
+ ENCODING("RST", ENCODING_FP)
ENCODING("GR16", ENCODING_RM)
ENCODING("GR32", ENCODING_RM)
ENCODING("GR32orGR64", ENCODING_RM)