The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being...

[oota-llvm.git] / utils / TableGen / X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 1198e5a9779a111131d66a5f6bf122d814741730..1df04224376c0f24d08d7ed5af132b8755e15c0e 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -230,7 +230,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   Prefix   = byteFromRec(Rec, "Prefix");
   Opcode   = byteFromRec(Rec, "Opcode");
   Form     = byteFromRec(Rec, "FormBits");
-  SegOvr   = byteFromRec(Rec, "SegOvrBits");
 
   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
@@ -248,6 +247,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
+  ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
 
   Name      = Rec->getName();
   AsmString = Rec->getValueAsString("AsmString");
@@ -274,11 +274,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
       break;
     }
   }
-  // FIXME: These instructions aren't marked as 64-bit in any way
-  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
-             Rec->getName().find("MOV64") != Name.npos ||
-             Rec->getName().find("PUSH64") != Name.npos ||
-             Rec->getName().find("POP64") != Name.npos;
 
   ShouldBeEmitted  = true;
 }
@@ -487,21 +482,13 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
 
   assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
 
-  if (Form == X86Local::Pseudo ||
-      (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
-       Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
+  if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
     return FILTER_STRONG;
 
 
   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
   // printed as a separate "instruction".
 
-  // Filter out instructions with segment override prefixes.
-  // They're too messy to handle now and we'll special case them if needed.
-
-  if (SegOvr)
-    return FILTER_STRONG;
-
 
   /////////////////
   // FILTER_WEAK
@@ -513,19 +500,9 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
   if (HasLockPrefix)
     return FILTER_WEAK;
 
-  // Filter out alternate forms of AVX instructions
-  if (Name.find("_alt") != Name.npos ||
-      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
-      Name.find("_64mr") != Name.npos ||
-      Name.find("rr64") != Name.npos)
-    return FILTER_WEAK;
-
   // Special cases.
 
-  if (Name == "PUSH64i16"         ||
-      Name == "MOVPQI2QImr"       ||
-      Name == "VMOVPQI2QImr"      ||
-      Name == "VMASKMOVDQU64")
+  if (Name == "VMASKMOVDQU64")
     return FILTER_WEAK;
 
   // XACQUIRE and XRELEASE reuse REPNE and REP respectively.