resolve fixme: we now infer the instruction-level 'isvariadic' bit

[oota-llvm.git] / utils / TableGen / RegisterInfoEmitter.h

diff --git a/utils/TableGen/RegisterInfoEmitter.h b/utils/TableGen/RegisterInfoEmitter.h
index 65a03303cddd21e5e3951d1603d6a63cbed30d25..1456b4f1ec70deffbf44820312e26c5159eee2bc 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.h
+++ b/utils/TableGen/RegisterInfoEmitter.h
@@ -1,5 +1,12 @@
 //===- RegisterInfoEmitter.h - Generate a Register File Desc. ---*- C++ -*-===//
 //
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
 // This tablegen backend is responsible for emitting a description of a target
 // register file for a code generator.  It uses instances of the Register,
 // RegisterAliases, and RegisterClass classes to gather this information.
@@ -11,19 +18,23 @@
 
 #include "TableGenBackend.h"
 
+namespace llvm {
+
 class RegisterInfoEmitter : public TableGenBackend {
   RecordKeeper &Records;
 public:
   RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
-  
+
   // run - Output the register file description, returning true on failure.
-  void run(std::ostream &o);
+  void run(raw_ostream &o);
 
   // runHeader - Emit a header fragment for the register info emitter.
-  void runHeader(std::ostream &o);
+  void runHeader(raw_ostream &o);
 
   // runEnums - Print out enum values for all of the registers.
-  void runEnums(std::ostream &o);
+  void runEnums(raw_ostream &o);
 };
 
+} // End llvm namespace
+
 #endif