#include "Record.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Streams.h"
-#include <set>
#include <algorithm>
+#include <set>
using namespace llvm;
// runEnums - Print out enum values for all of the registers.
-void RegisterInfoEmitter::runEnums(std::ostream &OS) {
+void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
CodeGenTarget Target;
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
OS << "} // End llvm namespace \n";
}
-void RegisterInfoEmitter::runHeader(std::ostream &OS) {
+void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
EmitSourceFileHeader("Register Information Header Fragment", OS);
CodeGenTarget Target;
const std::string &TargetName = Target.getName();
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n"
<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
+ << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
<< "};\n\n";
const std::vector<CodeGenRegisterClass> &RegisterClasses =
std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
if (R == S) {
- cerr << "Error: recursive sub-register relationship between"
- << " register " << getQualifiedName(R)
- << " and its sub-registers?\n";
+ errs() << "Error: recursive sub-register relationship between"
+ << " register " << getQualifiedName(R)
+ << " and its sub-registers?\n";
abort();
}
if (!SuperRegs[R].insert(S).second)
std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
if (R == S) {
- cerr << "Error: recursive sub-register relationship between"
- << " register " << getQualifiedName(R)
- << " and its sub-registers?\n";
+ errs() << "Error: recursive sub-register relationship between"
+ << " register " << getQualifiedName(R)
+ << " and its sub-registers?\n";
abort();
}
public:
RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
- : RegisterSubRegs(RS) {};
+ : RegisterSubRegs(RS) {}
bool operator()(Record *RegA, Record *RegB) {
// B is sub-register of A.
// RegisterInfoEmitter::run - Main register file description emitter.
//
-void RegisterInfoEmitter::run(std::ostream &OS) {
+void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target;
EmitSourceFileHeader("Register Information Source Fragment", OS);
// Emit the register list now.
OS << " // " << Name
<< " Register Class Value Types...\n"
- << " static const MVT " << Name
+ << " static const EVT " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
+ std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
+ // Emit the sub-register classes for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Sub-register Classes...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SubRegClasses[] = {\n ";
+
+ bool Empty = true;
+
+ for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
+ subrc != subrcMax; ++subrc) {
+ unsigned rc2 = 0, e2 = RegisterClasses.size();
+ for (; rc2 != e2; ++rc2) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+ if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+
+ std::map<unsigned, std::set<unsigned> >::iterator SCMI =
+ SuperRegClassMap.find(rc2);
+ if (SCMI == SuperRegClassMap.end()) {
+ SuperRegClassMap.insert(std::make_pair(rc2,
+ std::set<unsigned>()));
+ SCMI = SuperRegClassMap.find(rc2);
+ }
+ SCMI->second.insert(rc);
+ break;
+ }
+ }
+ if (rc2 == e2)
+ throw "Register Class member '" +
+ RC.SubRegClasses[subrc]->getName() +
+ "' is not a valid RegisterClass!";
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
+ // Emit the super-register classes for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Super-register Classes...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SuperRegClasses[] = {\n ";
+
+ bool Empty = true;
+ std::map<unsigned, std::set<unsigned> >::iterator I =
+ SuperRegClassMap.find(rc);
+ if (I != SuperRegClassMap.end()) {
+ for (std::set<unsigned>::iterator II = I->second.begin(),
+ EE = I->second.end(); II != EE; ++II) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+ }
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
OS << " // " << Name
<< " Register Class sub-classes...\n"
<< " static const TargetRegisterClass* const "
- << Name << "Subclasses [] = {\n ";
+ << Name << "Subclasses[] = {\n ";
bool Empty = true;
for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+
+ // RC2 is a sub-class of RC if it is a valid replacement for any
+ // instruction operand where an RC register is required. It must satisfy
+ // these conditions:
+ //
+ // 1. All RC2 registers are also in RC.
+ // 2. The RC2 spill size must not be smaller that the RC spill size.
+ // 3. RC2 spill alignment must be compatible with RC.
+ //
+ // Sub-classes are used to determine if a virtual register can be used
+ // as an instruction operand, or if it must be copied first.
+
if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
- RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
+ (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
+ RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
continue;
if (!Empty) OS << ", ";
OS << " // " << Name
<< " Register Class super-classes...\n"
<< " static const TargetRegisterClass* const "
- << Name << "Superclasses [] = {\n ";
+ << Name << "Superclasses[] = {\n ";
bool Empty = true;
std::map<unsigned, std::set<unsigned> >::iterator I =
OS << RC.getName() << "Class::" << RC.getName()
<< "Class() : TargetRegisterClass("
<< RC.getName() + "RegClassID" << ", "
+ << '\"' << RC.getName() << "\", "
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
+ << RC.getName() + "SubRegClasses" << ", "
+ << RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
for (unsigned j = 0, e = LI.size(); j != e; ++j) {
Record *Reg = LI[j];
if (RegisterAliases[R].count(Reg))
- cerr << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg)
- << " specified multiple times!\n";
+ errs() << "Warning: register alias between " << getQualifiedName(R)
+ << " and " << getQualifiedName(Reg)
+ << " specified multiple times!\n";
RegisterAliases[R].insert(Reg);
if (RegisterAliases[Reg].count(R))
- cerr << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg)
- << " specified multiple times!\n";
+ errs() << "Warning: register alias between " << getQualifiedName(R)
+ << " and " << getQualifiedName(Reg)
+ << " specified multiple times!\n";
RegisterAliases[Reg].insert(R);
}
}
for (unsigned j = 0, e = LI.size(); j != e; ++j) {
Record *SubReg = LI[j];
if (RegisterSubRegs[R].count(SubReg))
- cerr << "Warning: register " << getQualifiedName(SubReg)
- << " specified as a sub-register of " << getQualifiedName(R)
- << " multiple times!\n";
+ errs() << "Warning: register " << getQualifiedName(SubReg)
+ << " specified as a sub-register of " << getQualifiedName(R)
+ << " multiple times!\n";
addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
RegisterAliases);
}
delete [] SubregHashTable;
+
+ // Print the SuperregHashTable, a simple quadratically probed
+ // hash table for determining if a register is a super-register
+ // of another register.
+ unsigned NumSupRegs = 0;
+ RegNo.clear();
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ RegNo[Regs[i].TheDef] = i;
+ NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
+ }
+
+ unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
+ unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
+ std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
+
+ hashMisses = 0;
+
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record* R = Regs[i].TheDef;
+ for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
+ E = RegisterSuperRegs[R].end(); I != E; ++I) {
+ Record* RJ = *I;
+ // We have to increase the indices of both registers by one when
+ // computing the hash because, in the generated code, there
+ // will be an extra empty slot at register 0.
+ size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
+ unsigned ProbeAmt = 2;
+ while (SuperregHashTable[index*2] != ~0U &&
+ SuperregHashTable[index*2+1] != ~0U) {
+ index = (index + ProbeAmt) & (SuperregHashTableSize-1);
+ ProbeAmt += 2;
+
+ hashMisses++;
+ }
+
+ SuperregHashTable[index*2] = i;
+ SuperregHashTable[index*2+1] = RegNo[RJ];
+ }
+ }
+
+ OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
+
+ if (SuperregHashTableSize) {
+ std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
+
+ OS << " const unsigned SuperregHashTable[] = { ";
+ for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
+ if (i != 0)
+ // Insert spaces for nice formatting.
+ OS << " ";
+
+ if (SuperregHashTable[2*i] != ~0U) {
+ OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
+ << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+ }
+ }
+
+ unsigned Idx = SuperregHashTableSize*2-2;
+ if (SuperregHashTable[Idx] != ~0U) {
+ OS << " "
+ << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
+ << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
+ }
+
+ OS << " const unsigned SuperregHashTableSize = "
+ << SuperregHashTableSize << ";\n";
+ } else {
+ OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
+ << " const unsigned SuperregHashTableSize = 1;\n";
+ }
+
+ delete [] SuperregHashTable;
+
+
+ // Print the AliasHashTable, a simple quadratically probed
+ // hash table for determining if a register aliases another register.
+ unsigned NumAliases = 0;
+ RegNo.clear();
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ RegNo[Regs[i].TheDef] = i;
+ NumAliases += RegisterAliases[Regs[i].TheDef].size();
+ }
+
+ unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
+ unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
+ std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
+
+ hashMisses = 0;
+
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record* R = Regs[i].TheDef;
+ for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
+ E = RegisterAliases[R].end(); I != E; ++I) {
+ Record* RJ = *I;
+ // We have to increase the indices of both registers by one when
+ // computing the hash because, in the generated code, there
+ // will be an extra empty slot at register 0.
+ size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
+ unsigned ProbeAmt = 2;
+ while (AliasesHashTable[index*2] != ~0U &&
+ AliasesHashTable[index*2+1] != ~0U) {
+ index = (index + ProbeAmt) & (AliasesHashTableSize-1);
+ ProbeAmt += 2;
+
+ hashMisses++;
+ }
+
+ AliasesHashTable[index*2] = i;
+ AliasesHashTable[index*2+1] = RegNo[RJ];
+ }
+ }
+
+ OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
+
+ if (AliasesHashTableSize) {
+ std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
+
+ OS << " const unsigned AliasesHashTable[] = { ";
+ for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
+ if (i != 0)
+ // Insert spaces for nice formatting.
+ OS << " ";
+
+ if (AliasesHashTable[2*i] != ~0U) {
+ OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
+ << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+ }
+ }
+
+ unsigned Idx = AliasesHashTableSize*2-2;
+ if (AliasesHashTable[Idx] != ~0U) {
+ OS << " "
+ << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
+ << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
+ }
+
+ OS << " const unsigned AliasesHashTableSize = "
+ << AliasesHashTableSize << ";\n";
+ } else {
+ OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
+ << " const unsigned AliasesHashTableSize = 1;\n";
+ }
+
+ delete [] AliasesHashTable;
+
if (!RegisterAliases.empty())
OS << "\n\n // Register Alias Sets...\n";
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
OS << " { \"";
- if (!Reg.TheDef->getValueAsString("AsmName").empty())
- OS << Reg.TheDef->getValueAsString("AsmName");
- else
- OS << Reg.getName();
- OS << "\",\t\"";
OS << Reg.getName() << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
OS << Reg.getName() << "_AliasSet,\t";
std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
if (From.size() != To.size()) {
- cerr << "Error: register list and sub-register list not of equal length"
- << " in SubRegSet\n";
+ errs() << "Error: register list and sub-register list not of equal length"
+ << " in SubRegSet\n";
exit(1);
}
OS << " };\n";
OS << " return 0;\n";
OS << "}\n\n";
+
+ OS << "unsigned " << ClassName
+ << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
+ << " switch (RegNo) {\n"
+ << " default:\n return 0;\n";
+ for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
+ I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+ OS << " case " << getQualifiedName(I->first) << ":\n";
+ for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << " if (SubRegNo == "
+ << getQualifiedName((I->second)[i].second)
+ << ") return " << (I->second)[i].first << ";\n";
+ OS << " return 0;\n";
+ }
+ OS << " };\n";
+ OS << " return 0;\n";
+ OS << "}\n\n";
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
- << " SubregHashTable, SubregHashTableSize) {\n"
+ << " SubregHashTable, SubregHashTableSize,\n"
+ << " SuperregHashTable, SuperregHashTableSize,\n"
+ << " AliasesHashTable, AliasesHashTableSize) {\n"
<< "}\n\n";
// Collect all information about dwarf register numbers
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
- cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
- << "specified multiple times\n";
+ errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
+ << "specified multiple times\n";
DwarfRegNums[Reg] = RegNums;
}
projects / oota-llvm.git / blobdiff