//
//===----------------------------------------------------------------------===//
-#include "RegisterInfoEmitter.h"
-#include "CodeGenTarget.h"
#include "CodeGenRegisters.h"
-#include "Record.h"
-#include "llvm/ADT/StringExtras.h"
+#include "CodeGenTarget.h"
+#include "SequenceToOffsetTable.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/Format.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <set>
+#include <vector>
using namespace llvm;
+namespace {
+class RegisterInfoEmitter {
+ RecordKeeper &Records;
+public:
+ RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
+
+ // runEnums - Print out enum values for all of the registers.
+ void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
+
+ // runMCDesc - Print out MC register descriptions.
+ void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
+
+ // runTargetHeader - Emit a header fragment for the register info emitter.
+ void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
+ CodeGenRegBank &Bank);
+
+ // runTargetDesc - Output the target register and register file descriptions.
+ void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
+ CodeGenRegBank &Bank);
+
+ // run - Output the register file description.
+ void run(raw_ostream &o);
+
+private:
+ void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
+ bool isCtor);
+ void EmitRegMappingTables(raw_ostream &o,
+ const std::deque<CodeGenRegister> &Regs,
+ bool isCtor);
+ void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
+ const std::string &ClassName);
+ void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
+ const std::string &ClassName);
+};
+} // End anonymous namespace
+
// runEnums - Print out enum values for all of the registers.
-void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
- CodeGenTarget Target;
- const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
+void RegisterInfoEmitter::runEnums(raw_ostream &OS,
+ CodeGenTarget &Target, CodeGenRegBank &Bank) {
+ const auto &Registers = Bank.getRegisters();
+
+ // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
+ assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
- std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
+ std::string Namespace =
+ Registers.front().TheDef->getValueAsString("Namespace");
+
+ emitSourceFileHeader("Target Register Enum Values", OS);
+
+ OS << "\n#ifdef GET_REGINFO_ENUM\n";
+ OS << "#undef GET_REGINFO_ENUM\n";
- EmitSourceFileHeader("Target Register Enum Values", OS);
OS << "namespace llvm {\n\n";
+ OS << "class MCRegisterClass;\n"
+ << "extern const MCRegisterClass " << Namespace
+ << "MCRegisterClasses[];\n\n";
+
if (!Namespace.empty())
OS << "namespace " << Namespace << " {\n";
- OS << " enum {\n NoRegister,\n";
-
- for (unsigned i = 0, e = Registers.size(); i != e; ++i)
- OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
- OS << " };\n";
+ OS << "enum {\n NoRegister,\n";
+
+ for (const auto &Reg : Registers)
+ OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
+ assert(Registers.size() == Registers.back().EnumValue &&
+ "Register enum value mismatch!");
+ OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
+ OS << "};\n";
if (!Namespace.empty())
OS << "}\n";
- OS << "} // End llvm namespace \n";
-}
-void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
- EmitSourceFileHeader("Register Information Header Fragment", OS);
- CodeGenTarget Target;
- const std::string &TargetName = Target.getName();
- std::string ClassName = TargetName + "GenRegisterInfo";
+ const auto &RegisterClasses = Bank.getRegClasses();
+ if (!RegisterClasses.empty()) {
- OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
- OS << "#include <string>\n\n";
+ // RegisterClass enums are stored as uint16_t in the tables.
+ assert(RegisterClasses.size() <= 0xffff &&
+ "Too many register classes to fit in tables");
+
+ OS << "\n// Register classes\n";
+ if (!Namespace.empty())
+ OS << "namespace " << Namespace << " {\n";
+ OS << "enum {\n";
+ for (const auto *RC : RegisterClasses)
+ OS << " " << RC->getName() << "RegClassID"
+ << " = " << RC->EnumValue << ",\n";
+ OS << "\n };\n";
+ if (!Namespace.empty())
+ OS << "}\n";
+ }
- OS << "namespace llvm {\n\n";
+ const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
+ // If the only definition is the default NoRegAltName, we don't need to
+ // emit anything.
+ if (RegAltNameIndices.size() > 1) {
+ OS << "\n// Register alternate name indices\n";
+ if (!Namespace.empty())
+ OS << "namespace " << Namespace << " {\n";
+ OS << "enum {\n";
+ for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
+ OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
+ OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
+ OS << "};\n";
+ if (!Namespace.empty())
+ OS << "}\n";
+ }
- OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
- << " explicit " << ClassName
- << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
- << " virtual int getDwarfRegNumFull(unsigned RegNum, "
- << "unsigned Flavour) const;\n"
- << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
- << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
- << " { return false; }\n"
- << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
- << "};\n\n";
+ auto &SubRegIndices = Bank.getSubRegIndices();
+ if (!SubRegIndices.empty()) {
+ OS << "\n// Subregister indices\n";
+ std::string Namespace = SubRegIndices.front().getNamespace();
+ if (!Namespace.empty())
+ OS << "namespace " << Namespace << " {\n";
+ OS << "enum {\n NoSubRegister,\n";
+ unsigned i = 0;
+ for (const auto &Idx : SubRegIndices)
+ OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
+ OS << " NUM_TARGET_SUBREGS\n};\n";
+ if (!Namespace.empty())
+ OS << "}\n";
+ }
- const std::vector<CodeGenRegisterClass> &RegisterClasses =
- Target.getRegisterClasses();
+ OS << "} // End llvm namespace\n";
+ OS << "#endif // GET_REGINFO_ENUM\n\n";
+}
- if (!RegisterClasses.empty()) {
- OS << "namespace " << RegisterClasses[0].Namespace
- << " { // Register classes\n";
-
- OS << " enum {\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- if (i) OS << ",\n";
- OS << " " << RegisterClasses[i].getName() << "RegClassID";
- OS << " = " << (i+1);
+static void printInt(raw_ostream &OS, int Val) {
+ OS << Val;
+}
+
+static const char *getMinimalTypeForRange(uint64_t Range) {
+ assert(Range < 0xFFFFFFFFULL && "Enum too large");
+ if (Range > 0xFFFF)
+ return "uint32_t";
+ if (Range > 0xFF)
+ return "uint16_t";
+ return "uint8_t";
+}
+
+void RegisterInfoEmitter::
+EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
+ const std::string &ClassName) {
+ unsigned NumRCs = RegBank.getRegClasses().size();
+ unsigned NumSets = RegBank.getNumRegPressureSets();
+
+ OS << "/// Get the weight in units of pressure for this register class.\n"
+ << "const RegClassWeight &" << ClassName << "::\n"
+ << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
+ << " static const RegClassWeight RCWeightTable[] = {\n";
+ for (const auto *RCP : RegBank.getRegClasses()) {
+ const CodeGenRegisterClass &RC = *RCP;
+ const CodeGenRegister::Set &Regs = RC.getMembers();
+ if (Regs.empty())
+ OS << " {0, 0";
+ else {
+ std::vector<unsigned> RegUnits;
+ RC.buildRegUnitSet(RegUnits);
+ OS << " {" << (*Regs.begin())->getWeight(RegBank)
+ << ", " << RegBank.getRegUnitSetWeight(RegUnits);
}
- OS << "\n };\n\n";
+ OS << "}, \t// " << RC.getName() << "\n";
+ }
+ OS << " };\n"
+ << " return RCWeightTable[RC->getID()];\n"
+ << "}\n\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- const std::string &Name = RegisterClasses[i].getName();
+ // Reasonable targets (not ARMv7) have unit weight for all units, so don't
+ // bother generating a table.
+ bool RegUnitsHaveUnitWeight = true;
+ for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
+ UnitIdx < UnitEnd; ++UnitIdx) {
+ if (RegBank.getRegUnit(UnitIdx).Weight > 1)
+ RegUnitsHaveUnitWeight = false;
+ }
+ OS << "/// Get the weight in units of pressure for this register unit.\n"
+ << "unsigned " << ClassName << "::\n"
+ << "getRegUnitWeight(unsigned RegUnit) const {\n"
+ << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
+ << " && \"invalid register unit\");\n";
+ if (!RegUnitsHaveUnitWeight) {
+ OS << " static const uint8_t RUWeightTable[] = {\n ";
+ for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
+ UnitIdx < UnitEnd; ++UnitIdx) {
+ const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
+ assert(RU.Weight < 256 && "RegUnit too heavy");
+ OS << RU.Weight << ", ";
+ }
+ OS << "};\n"
+ << " return RUWeightTable[RegUnit];\n";
+ }
+ else {
+ OS << " // All register units have unit weight.\n"
+ << " return 1;\n";
+ }
+ OS << "}\n\n";
- // Output the register class definition.
- OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
- << " " << Name << "Class();\n"
- << RegisterClasses[i].MethodProtos << " };\n";
+ OS << "\n"
+ << "// Get the number of dimensions of register pressure.\n"
+ << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
+ << " return " << NumSets << ";\n}\n\n";
+
+ OS << "// Get the name of this register unit pressure set.\n"
+ << "const char *" << ClassName << "::\n"
+ << "getRegPressureSetName(unsigned Idx) const {\n"
+ << " static const char *PressureNameTable[] = {\n";
+ unsigned MaxRegUnitWeight = 0;
+ for (unsigned i = 0; i < NumSets; ++i ) {
+ const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
+ MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
+ OS << " \"" << RegUnits.Name << "\",\n";
+ }
+ OS << " nullptr };\n"
+ << " return PressureNameTable[Idx];\n"
+ << "}\n\n";
- // Output the extern for the instance.
- OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
- // Output the extern for the pointer to the instance (should remove).
- OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
- << Name << "RegClass;\n";
+ OS << "// Get the register unit pressure limit for this dimension.\n"
+ << "// This limit must be adjusted dynamically for reserved registers.\n"
+ << "unsigned " << ClassName << "::\n"
+ << "getRegPressureSetLimit(unsigned Idx) const {\n"
+ << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
+ << " PressureLimitTable[] = {\n";
+ for (unsigned i = 0; i < NumSets; ++i ) {
+ const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
+ OS << " " << RegUnits.Weight << ", \t// " << i << ": "
+ << RegUnits.Name << "\n";
+ }
+ OS << " };\n"
+ << " return PressureLimitTable[Idx];\n"
+ << "}\n\n";
+
+ SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
+
+ // This table may be larger than NumRCs if some register units needed a list
+ // of unit sets that did not correspond to a register class.
+ unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
+ std::vector<std::vector<int>> PSets(NumRCUnitSets);
+
+ for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
+ ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
+ PSets[i].reserve(PSetIDs.size());
+ for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
+ PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
+ PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
}
- OS << "} // end of namespace " << TargetName << "\n\n";
+ std::sort(PSets[i].begin(), PSets[i].end());
+ PSetsSeqs.add(PSets[i]);
}
- OS << "} // End llvm namespace \n";
-}
-bool isSubRegisterClass(const CodeGenRegisterClass &RC,
- std::set<Record*> &RegSet) {
- for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
- Record *Reg = RC.Elements[i];
- if (!RegSet.count(Reg))
- return false;
+ PSetsSeqs.layout();
+
+ OS << "/// Table of pressure sets per register class or unit.\n"
+ << "static const int RCSetsTable[] = {\n";
+ PSetsSeqs.emit(OS, printInt, "-1");
+ OS << "};\n\n";
+
+ OS << "/// Get the dimensions of register pressure impacted by this "
+ << "register class.\n"
+ << "/// Returns a -1 terminated array of pressure set IDs\n"
+ << "const int* " << ClassName << "::\n"
+ << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
+ OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
+ << " RCSetStartTable[] = {\n ";
+ for (unsigned i = 0, e = NumRCs; i != e; ++i) {
+ OS << PSetsSeqs.get(PSets[i]) << ",";
}
- return true;
+ OS << "};\n"
+ << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
+ << "}\n\n";
+
+ OS << "/// Get the dimensions of register pressure impacted by this "
+ << "register unit.\n"
+ << "/// Returns a -1 terminated array of pressure set IDs\n"
+ << "const int* " << ClassName << "::\n"
+ << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
+ << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
+ << " && \"invalid register unit\");\n";
+ OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
+ << " RUSetStartTable[] = {\n ";
+ for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
+ UnitIdx < UnitEnd; ++UnitIdx) {
+ OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
+ << ",";
+ }
+ OS << "};\n"
+ << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
+ << "}\n\n";
}
-static void addSuperReg(Record *R, Record *S,
- std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
- std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
- std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
- if (R == S) {
- errs() << "Error: recursive sub-register relationship between"
- << " register " << getQualifiedName(R)
- << " and its sub-registers?\n";
- abort();
- }
- if (!SuperRegs[R].insert(S).second)
+void RegisterInfoEmitter::EmitRegMappingTables(
+ raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
+ // Collect all information about dwarf register numbers
+ typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
+ DwarfRegNumsMapTy DwarfRegNums;
+
+ // First, just pull all provided information to the map
+ unsigned maxLength = 0;
+ for (auto &RE : Regs) {
+ Record *Reg = RE.TheDef;
+ std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
+ maxLength = std::max((size_t)maxLength, RegNums.size());
+ if (DwarfRegNums.count(Reg))
+ PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
+ getQualifiedName(Reg) + "specified multiple times");
+ DwarfRegNums[Reg] = RegNums;
+ }
+
+ if (!maxLength)
return;
- SubRegs[S].insert(R);
- Aliases[R].insert(S);
- Aliases[S].insert(R);
- if (SuperRegs.count(S))
- for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
- E = SuperRegs[S].end(); I != E; ++I)
- addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
+
+ // Now we know maximal length of number list. Append -1's, where needed
+ for (DwarfRegNumsMapTy::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
+ for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
+ I->second.push_back(-1);
+
+ std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
+
+ OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
+
+ // Emit reverse information about the dwarf register numbers.
+ for (unsigned j = 0; j < 2; ++j) {
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
+ OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
+ OS << i << "Dwarf2L[]";
+
+ if (!isCtor) {
+ OS << " = {\n";
+
+ // Store the mapping sorted by the LLVM reg num so lookup can be done
+ // with a binary search.
+ std::map<uint64_t, Record*> Dwarf2LMap;
+ for (DwarfRegNumsMapTy::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
+ int DwarfRegNo = I->second[i];
+ if (DwarfRegNo < 0)
+ continue;
+ Dwarf2LMap[DwarfRegNo] = I->first;
+ }
+
+ for (std::map<uint64_t, Record*>::iterator
+ I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
+ OS << " { " << I->first << "U, " << getQualifiedName(I->second)
+ << " },\n";
+
+ OS << "};\n";
+ } else {
+ OS << ";\n";
+ }
+
+ // We have to store the size in a const global, it's used in multiple
+ // places.
+ OS << "extern const unsigned " << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
+ if (!isCtor)
+ OS << " = array_lengthof(" << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
+ << "Dwarf2L);\n\n";
+ else
+ OS << ";\n\n";
+ }
+ }
+
+ for (auto &RE : Regs) {
+ Record *Reg = RE.TheDef;
+ const RecordVal *V = Reg->getValue("DwarfAlias");
+ if (!V || !V->getValue())
+ continue;
+
+ DefInit *DI = cast<DefInit>(V->getValue());
+ Record *Alias = DI->getDef();
+ DwarfRegNums[Reg] = DwarfRegNums[Alias];
+ }
+
+ // Emit information about the dwarf register numbers.
+ for (unsigned j = 0; j < 2; ++j) {
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
+ OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
+ OS << i << "L2Dwarf[]";
+ if (!isCtor) {
+ OS << " = {\n";
+ // Store the mapping sorted by the Dwarf reg num so lookup can be done
+ // with a binary search.
+ for (DwarfRegNumsMapTy::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
+ int RegNo = I->second[i];
+ if (RegNo == -1) // -1 is the default value, don't emit a mapping.
+ continue;
+
+ OS << " { " << getQualifiedName(I->first) << ", " << RegNo
+ << "U },\n";
+ }
+ OS << "};\n";
+ } else {
+ OS << ";\n";
+ }
+
+ // We have to store the size in a const global, it's used in multiple
+ // places.
+ OS << "extern const unsigned " << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
+ if (!isCtor)
+ OS << " = array_lengthof(" << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
+ else
+ OS << ";\n\n";
+ }
+ }
}
-static void addSubSuperReg(Record *R, Record *S,
- std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
- std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
- std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
- if (R == S) {
- errs() << "Error: recursive sub-register relationship between"
- << " register " << getQualifiedName(R)
- << " and its sub-registers?\n";
- abort();
+void RegisterInfoEmitter::EmitRegMapping(
+ raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
+ // Emit the initializer so the tables from EmitRegMappingTables get wired up
+ // to the MCRegisterInfo object.
+ unsigned maxLength = 0;
+ for (auto &RE : Regs) {
+ Record *Reg = RE.TheDef;
+ maxLength = std::max((size_t)maxLength,
+ Reg->getValueAsListOfInts("DwarfNumbers").size());
}
- if (!SubRegs[R].insert(S).second)
+ if (!maxLength)
return;
- addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
- Aliases[R].insert(S);
- Aliases[S].insert(R);
- if (SubRegs.count(S))
- for (std::set<Record*>::iterator I = SubRegs[S].begin(),
- E = SubRegs[S].end(); I != E; ++I)
- addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
+
+ std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
+
+ // Emit reverse information about the dwarf register numbers.
+ for (unsigned j = 0; j < 2; ++j) {
+ OS << " switch (";
+ if (j == 0)
+ OS << "DwarfFlavour";
+ else
+ OS << "EHFlavour";
+ OS << ") {\n"
+ << " default:\n"
+ << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
+
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << " case " << i << ":\n";
+ OS << " ";
+ if (!isCtor)
+ OS << "RI->";
+ std::string Tmp;
+ raw_string_ostream(Tmp) << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
+ << "Dwarf2L";
+ OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
+ if (j == 0)
+ OS << "false";
+ else
+ OS << "true";
+ OS << ");\n";
+ OS << " break;\n";
+ }
+ OS << " }\n";
+ }
+
+ // Emit information about the dwarf register numbers.
+ for (unsigned j = 0; j < 2; ++j) {
+ OS << " switch (";
+ if (j == 0)
+ OS << "DwarfFlavour";
+ else
+ OS << "EHFlavour";
+ OS << ") {\n"
+ << " default:\n"
+ << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
+
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << " case " << i << ":\n";
+ OS << " ";
+ if (!isCtor)
+ OS << "RI->";
+ std::string Tmp;
+ raw_string_ostream(Tmp) << Namespace
+ << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
+ << "L2Dwarf";
+ OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
+ if (j == 0)
+ OS << "false";
+ else
+ OS << "true";
+ OS << ");\n";
+ OS << " break;\n";
+ }
+ OS << " }\n";
+ }
}
-class RegisterSorter {
-private:
- std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
+// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
+// Width is the number of bits per hex number.
+static void printBitVectorAsHex(raw_ostream &OS,
+ const BitVector &Bits,
+ unsigned Width) {
+ assert(Width <= 32 && "Width too large");
+ unsigned Digits = (Width + 3) / 4;
+ for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
+ unsigned Value = 0;
+ for (unsigned j = 0; j != Width && i + j != e; ++j)
+ Value |= Bits.test(i + j) << j;
+ OS << format("0x%0*x, ", Digits, Value);
+ }
+}
+// Helper to emit a set of bits into a constant byte array.
+class BitVectorEmitter {
+ BitVector Values;
public:
- RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
- : RegisterSubRegs(RS) {};
+ void add(unsigned v) {
+ if (v >= Values.size())
+ Values.resize(((v/8)+1)*8); // Round up to the next byte.
+ Values[v] = true;
+ }
- bool operator()(Record *RegA, Record *RegB) {
- // B is sub-register of A.
- return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
+ void print(raw_ostream &OS) {
+ printBitVectorAsHex(OS, Values, 8);
}
};
-// RegisterInfoEmitter::run - Main register file description emitter.
+static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
+ OS << getEnumName(VT);
+}
+
+static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
+ OS << Idx->EnumValue;
+}
+
+// Differentially encoded register and regunit lists allow for better
+// compression on regular register banks. The sequence is computed from the
+// differential list as:
//
-void RegisterInfoEmitter::run(raw_ostream &OS) {
- CodeGenTarget Target;
- EmitSourceFileHeader("Register Information Source Fragment", OS);
+// out[0] = InitVal;
+// out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
+//
+// The initial value depends on the specific list. The list is terminated by a
+// 0 differential which means we can't encode repeated elements.
+
+typedef SmallVector<uint16_t, 4> DiffVec;
+
+// Differentially encode a sequence of numbers into V. The starting value and
+// terminating 0 are not added to V, so it will have the same size as List.
+static
+DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
+ assert(V.empty() && "Clear DiffVec before diffEncode.");
+ uint16_t Val = uint16_t(InitVal);
+ for (unsigned i = 0; i != List.size(); ++i) {
+ uint16_t Cur = List[i];
+ V.push_back(Cur - Val);
+ Val = Cur;
+ }
+ return V;
+}
- OS << "namespace llvm {\n\n";
+template<typename Iter>
+static
+DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
+ assert(V.empty() && "Clear DiffVec before diffEncode.");
+ uint16_t Val = uint16_t(InitVal);
+ for (Iter I = Begin; I != End; ++I) {
+ uint16_t Cur = (*I)->EnumValue;
+ V.push_back(Cur - Val);
+ Val = Cur;
+ }
+ return V;
+}
- // Start out by emitting each of the register classes... to do this, we build
- // a set of registers which belong to a register class, this is to ensure that
- // each register is only in a single register class.
+static void printDiff16(raw_ostream &OS, uint16_t Val) {
+ OS << Val;
+}
+
+// Try to combine Idx's compose map into Vec if it is compatible.
+// Return false if it's not possible.
+static bool combine(const CodeGenSubRegIndex *Idx,
+ SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
+ const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
+ for (CodeGenSubRegIndex::CompMap::const_iterator
+ I = Map.begin(), E = Map.end(); I != E; ++I) {
+ CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
+ if (Entry && Entry != I->second)
+ return false;
+ }
+
+ // All entries are compatible. Make it so.
+ for (CodeGenSubRegIndex::CompMap::const_iterator
+ I = Map.begin(), E = Map.end(); I != E; ++I)
+ Vec[I->first->EnumValue - 1] = I->second;
+ return true;
+}
+
+void
+RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
+ CodeGenRegBank &RegBank,
+ const std::string &ClName) {
+ const auto &SubRegIndices = RegBank.getSubRegIndices();
+ OS << "unsigned " << ClName
+ << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
+
+ // Many sub-register indexes are composition-compatible, meaning that
//
- const std::vector<CodeGenRegisterClass> &RegisterClasses =
- Target.getRegisterClasses();
+ // compose(IdxA, IdxB) == compose(IdxA', IdxB)
+ //
+ // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
+ // The illegal entries can be use as wildcards to compress the table further.
+
+ // Map each Sub-register index to a compatible table row.
+ SmallVector<unsigned, 4> RowMap;
+ SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
+
+ auto SubRegIndicesSize =
+ std::distance(SubRegIndices.begin(), SubRegIndices.end());
+ for (const auto &Idx : SubRegIndices) {
+ unsigned Found = ~0u;
+ for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
+ if (combine(&Idx, Rows[r])) {
+ Found = r;
+ break;
+ }
+ }
+ if (Found == ~0u) {
+ Found = Rows.size();
+ Rows.resize(Found + 1);
+ Rows.back().resize(SubRegIndicesSize);
+ combine(&Idx, Rows.back());
+ }
+ RowMap.push_back(Found);
+ }
+
+ // Output the row map if there is multiple rows.
+ if (Rows.size() > 1) {
+ OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
+ << SubRegIndicesSize << "] = {\n ";
+ for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
+ OS << RowMap[i] << ", ";
+ OS << "\n };\n";
+ }
+
+ // Output the rows.
+ OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
+ << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
+ for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
+ OS << " { ";
+ for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
+ if (Rows[r][i])
+ OS << Rows[r][i]->EnumValue << ", ";
+ else
+ OS << "0, ";
+ OS << "},\n";
+ }
+ OS << " };\n\n";
+
+ OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
+ << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
+ if (Rows.size() > 1)
+ OS << " return Rows[RowMap[IdxA]][IdxB];\n";
+ else
+ OS << " return Rows[0][IdxB];\n";
+ OS << "}\n\n";
+}
+
+//
+// runMCDesc - Print out MC register descriptions.
+//
+void
+RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank) {
+ emitSourceFileHeader("MC Register Information", OS);
+
+ OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
+ OS << "#undef GET_REGINFO_MC_DESC\n";
+
+ const auto &Regs = RegBank.getRegisters();
+
+ auto &SubRegIndices = RegBank.getSubRegIndices();
+ // The lists of sub-registers and super-registers go in the same array. That
+ // allows us to share suffixes.
+ typedef std::vector<const CodeGenRegister*> RegVec;
+
+ // Differentially encoded lists.
+ SequenceToOffsetTable<DiffVec> DiffSeqs;
+ SmallVector<DiffVec, 4> SubRegLists(Regs.size());
+ SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
+ SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
+ SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
+
+ // Keep track of sub-register names as well. These are not differentially
+ // encoded.
+ typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
+ SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
+ SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
+
+ SequenceToOffsetTable<std::string> RegStrings;
+
+ // Precompute register lists for the SequenceToOffsetTable.
+ unsigned i = 0;
+ for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
+ const auto &Reg = *I;
+ RegStrings.add(Reg.getName());
+
+ // Compute the ordered sub-register list.
+ SetVector<const CodeGenRegister*> SR;
+ Reg.addSubRegsPreOrder(SR, RegBank);
+ diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
+ DiffSeqs.add(SubRegLists[i]);
+
+ // Compute the corresponding sub-register indexes.
+ SubRegIdxVec &SRIs = SubRegIdxLists[i];
+ for (unsigned j = 0, je = SR.size(); j != je; ++j)
+ SRIs.push_back(Reg.getSubRegIndex(SR[j]));
+ SubRegIdxSeqs.add(SRIs);
+
+ // Super-registers are already computed.
+ const RegVec &SuperRegList = Reg.getSuperRegs();
+ diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
+ SuperRegList.end());
+ DiffSeqs.add(SuperRegLists[i]);
+
+ // Differentially encode the register unit list, seeded by register number.
+ // First compute a scale factor that allows more diff-lists to be reused:
+ //
+ // D0 -> (S0, S1)
+ // D1 -> (S2, S3)
+ //
+ // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
+ // value for the differential decoder is the register number multiplied by
+ // the scale.
+ //
+ // Check the neighboring registers for arithmetic progressions.
+ unsigned ScaleA = ~0u, ScaleB = ~0u;
+ ArrayRef<unsigned> RUs = Reg.getNativeRegUnits();
+ if (I != Regs.begin() &&
+ std::prev(I)->getNativeRegUnits().size() == RUs.size())
+ ScaleB = RUs.front() - std::prev(I)->getNativeRegUnits().front();
+ if (std::next(I) != Regs.end() &&
+ std::next(I)->getNativeRegUnits().size() == RUs.size())
+ ScaleA = std::next(I)->getNativeRegUnits().front() - RUs.front();
+ unsigned Scale = std::min(ScaleB, ScaleA);
+ // Default the scale to 0 if it can't be encoded in 4 bits.
+ if (Scale >= 16)
+ Scale = 0;
+ RegUnitInitScale[i] = Scale;
+ DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
+ ++i;
+ }
+
+ // Compute the final layout of the sequence table.
+ DiffSeqs.layout();
+ SubRegIdxSeqs.layout();
+
+ OS << "namespace llvm {\n\n";
+
+ const std::string &TargetName = Target.getName();
+
+ // Emit the shared table of differential lists.
+ OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
+ DiffSeqs.emit(OS, printDiff16);
+ OS << "};\n\n";
+
+ // Emit the table of sub-register indexes.
+ OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
+ SubRegIdxSeqs.emit(OS, printSubRegIndex);
+ OS << "};\n\n";
+
+ // Emit the table of sub-register index sizes.
+ OS << "extern const MCRegisterInfo::SubRegCoveredBits "
+ << TargetName << "SubRegIdxRanges[] = {\n";
+ OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
+ for (const auto &Idx : SubRegIndices) {
+ OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
+ << Idx.getName() << "\n";
+ }
+ OS << "};\n\n";
+
+ // Emit the string table.
+ RegStrings.layout();
+ OS << "extern const char " << TargetName << "RegStrings[] = {\n";
+ RegStrings.emit(OS, printChar);
+ OS << "};\n\n";
+
+ OS << "extern const MCRegisterDesc " << TargetName
+ << "RegDesc[] = { // Descriptors\n";
+ OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
+
+ // Emit the register descriptors now.
+ i = 0;
+ for (const auto &Reg : Regs) {
+ OS << " { " << RegStrings.get(Reg.getName()) << ", "
+ << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
+ << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
+ << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << " },\n";
+ ++i;
+ }
+ OS << "};\n\n"; // End of register descriptors...
+
+ // Emit the table of register unit roots. Each regunit has one or two root
+ // registers.
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
+ for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
+ ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
+ assert(!Roots.empty() && "All regunits must have a root register.");
+ assert(Roots.size() <= 2 && "More than two roots not supported yet.");
+ OS << " { " << getQualifiedName(Roots.front()->TheDef);
+ for (unsigned r = 1; r != Roots.size(); ++r)
+ OS << ", " << getQualifiedName(Roots[r]->TheDef);
+ OS << " },\n";
+ }
+ OS << "};\n\n";
+
+ const auto &RegisterClasses = RegBank.getRegClasses();
// Loop over all of the register classes... emitting each one.
OS << "namespace { // Register classes...\n";
- // RegClassesBelongedTo - Keep track of which register classes each reg
- // belongs to.
- std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
+ SequenceToOffsetTable<std::string> RegClassStrings;
// Emit the register enum value arrays for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ ArrayRef<Record*> Order = RC.getOrder();
// Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
+ std::string Name = RC.getName();
+
+ RegClassStrings.add(Name);
+
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
- << " static const unsigned " << Name
+ << " const MCPhysReg " << Name
<< "[] = {\n ";
- for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
- Record *Reg = RC.Elements[i];
+ for (unsigned i = 0, e = Order.size(); i != e; ++i) {
+ Record *Reg = Order[i];
OS << getQualifiedName(Reg) << ", ";
+ }
+ OS << "\n };\n\n";
- // Keep track of which regclasses this register is in.
- RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
+ OS << " // " << Name << " Bit set.\n"
+ << " const uint8_t " << Name
+ << "Bits[] = {\n ";
+ BitVectorEmitter BVE;
+ for (unsigned i = 0, e = Order.size(); i != e; ++i) {
+ Record *Reg = Order[i];
+ BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
}
+ BVE.print(OS);
OS << "\n };\n\n";
+
}
+ OS << "}\n\n";
- // Emit the ValueType arrays for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName() + "VTs";
-
- // Emit the register list now.
- OS << " // " << Name
- << " Register Class Value Types...\n"
- << " static const MVT " << Name
- << "[] = {\n ";
- for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
- OS << getEnumName(RC.VTs[i]) << ", ";
- OS << "MVT::Other\n };\n\n";
+ RegClassStrings.layout();
+ OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
+ RegClassStrings.emit(OS, printChar);
+ OS << "};\n\n";
+
+ OS << "extern const MCRegisterClass " << TargetName
+ << "MCRegisterClasses[] = {\n";
+
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+
+ // Asserts to make sure values will fit in table assuming types from
+ // MCRegisterInfo.h
+ assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
+ assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
+ assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
+
+ OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
+ << RegClassStrings.get(RC.getName()) << ", "
+ << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
+ << RC.getQualifiedName() + "RegClassID" << ", "
+ << RC.SpillSize/8 << ", "
+ << RC.SpillAlignment/8 << ", "
+ << RC.CopyCost << ", "
+ << RC.Allocatable << " },\n";
}
- OS << "} // end anonymous namespace\n\n";
-
- // Now that all of the structs have been emitted, emit the instances.
- if (!RegisterClasses.empty()) {
- OS << "namespace " << RegisterClasses[0].Namespace
- << " { // Register class instances\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
- OS << " " << RegisterClasses[i].getName() << "Class\t"
- << RegisterClasses[i].getName() << "RegClass;\n";
-
- std::map<unsigned, std::set<unsigned> > SuperClassMap;
- std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
- OS << "\n";
-
- // Emit the sub-register classes for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
- OS << " // " << Name
- << " Sub-register Classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "SubRegClasses [] = {\n ";
-
- bool Empty = true;
-
- for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
- subrc != subrcMax; ++subrc) {
- unsigned rc2 = 0, e2 = RegisterClasses.size();
- for (; rc2 != e2; ++rc2) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
- if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
- if (!Empty)
- OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
-
- std::map<unsigned, std::set<unsigned> >::iterator SCMI =
- SuperRegClassMap.find(rc2);
- if (SCMI == SuperRegClassMap.end()) {
- SuperRegClassMap.insert(std::make_pair(rc2,
- std::set<unsigned>()));
- SCMI = SuperRegClassMap.find(rc2);
- }
- SCMI->second.insert(rc);
- break;
- }
- }
- if (rc2 == e2)
- throw "Register Class member '" +
- RC.SubRegClasses[subrc]->getName() +
- "' is not a valid RegisterClass!";
- }
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
+ OS << "};\n\n";
+
+ EmitRegMappingTables(OS, Regs, false);
+
+ // Emit Reg encoding table
+ OS << "extern const uint16_t " << TargetName;
+ OS << "RegEncodingTable[] = {\n";
+ // Add entry for NoRegister
+ OS << " 0,\n";
+ for (const auto &RE : Regs) {
+ Record *Reg = RE.TheDef;
+ BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
+ uint64_t Value = 0;
+ for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
+ if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
+ Value |= (uint64_t)B->getValue() << b;
}
+ OS << " " << Value << ",\n";
+ }
+ OS << "};\n"; // End of HW encoding table
+
+ // MCRegisterInfo initialization routine.
+ OS << "static inline void Init" << TargetName
+ << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
+ << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
+ "{\n"
+ << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
+ << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
+ << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
+ << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
+ << TargetName << "RegStrings, " << TargetName << "RegClassStrings, "
+ << TargetName << "SubRegIdxLists, "
+ << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
+ << TargetName << "SubRegIdxRanges, " << TargetName
+ << "RegEncodingTable);\n\n";
+
+ EmitRegMapping(OS, Regs, false);
- // Emit the super-register classes for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
- OS << " // " << Name
- << " Super-register Classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "SuperRegClasses [] = {\n ";
-
- bool Empty = true;
- std::map<unsigned, std::set<unsigned> >::iterator I =
- SuperRegClassMap.find(rc);
- if (I != SuperRegClassMap.end()) {
- for (std::set<unsigned>::iterator II = I->second.begin(),
- EE = I->second.end(); II != EE; ++II) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
- if (!Empty)
- OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
- }
- }
+ OS << "}\n\n";
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
- }
+ OS << "} // End llvm namespace\n";
+ OS << "#endif // GET_REGINFO_MC_DESC\n\n";
+}
- // Emit the sub-classes array for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
+void
+RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank) {
+ emitSourceFileHeader("Register Information Header Fragment", OS);
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
+ OS << "\n#ifdef GET_REGINFO_HEADER\n";
+ OS << "#undef GET_REGINFO_HEADER\n";
- std::set<Record*> RegSet;
- for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
- Record *Reg = RC.Elements[i];
- RegSet.insert(Reg);
- }
+ const std::string &TargetName = Target.getName();
+ std::string ClassName = TargetName + "GenRegisterInfo";
- OS << " // " << Name
- << " Register Class sub-classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "Subclasses [] = {\n ";
-
- bool Empty = true;
- for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
-
- // RC2 is a sub-class of RC if it is a valid replacement for any
- // instruction operand where an RC register is required. It must satisfy
- // these conditions:
- //
- // 1. All RC2 registers are also in RC.
- // 2. The RC2 spill size must not be smaller that the RC spill size.
- // 3. RC2 spill alignment must be compatible with RC.
- //
- // Sub-classes are used to determine if a virtual register can be used
- // as an instruction operand, or if it must be copied first.
-
- if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
- (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
- RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
- continue;
-
- if (!Empty) OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
-
- std::map<unsigned, std::set<unsigned> >::iterator SCMI =
- SuperClassMap.find(rc2);
- if (SCMI == SuperClassMap.end()) {
- SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
- SCMI = SuperClassMap.find(rc2);
- }
- SCMI->second.insert(rc);
- }
+ OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
- }
+ OS << "namespace llvm {\n\n";
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
- OS << " // " << Name
- << " Register Class super-classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "Superclasses [] = {\n ";
-
- bool Empty = true;
- std::map<unsigned, std::set<unsigned> >::iterator I =
- SuperClassMap.find(rc);
- if (I != SuperClassMap.end()) {
- for (std::set<unsigned>::iterator II = I->second.begin(),
- EE = I->second.end(); II != EE; ++II) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
- if (!Empty) OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
- }
- }
+ OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
+ << " explicit " << ClassName
+ << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
+ << " bool needsStackRealignment(const MachineFunction &) const override\n"
+ << " { return false; }\n";
+ if (!RegBank.getSubRegIndices().empty()) {
+ OS << " unsigned composeSubRegIndicesImpl"
+ << "(unsigned, unsigned) const override;\n"
+ << " const TargetRegisterClass *getSubClassWithSubReg"
+ << "(const TargetRegisterClass*, unsigned) const override;\n";
+ }
+ OS << " const RegClassWeight &getRegClassWeight("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
+ << " unsigned getNumRegPressureSets() const override;\n"
+ << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
+ << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
+ << " const int *getRegClassPressureSets("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " const int *getRegUnitPressureSets("
+ << "unsigned RegUnit) const override;\n"
+ << "};\n\n";
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
- }
+ const auto &RegisterClasses = RegBank.getRegClasses();
+ if (!RegisterClasses.empty()) {
+ OS << "namespace " << RegisterClasses.front()->Namespace
+ << " { // Register classes\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- const CodeGenRegisterClass &RC = RegisterClasses[i];
- OS << RC.MethodBodies << "\n";
- OS << RC.getName() << "Class::" << RC.getName()
- << "Class() : TargetRegisterClass("
- << RC.getName() + "RegClassID" << ", "
- << '\"' << RC.getName() << "\", "
- << RC.getName() + "VTs" << ", "
- << RC.getName() + "Subclasses" << ", "
- << RC.getName() + "Superclasses" << ", "
- << RC.getName() + "SubRegClasses" << ", "
- << RC.getName() + "SuperRegClasses" << ", "
- << RC.SpillSize/8 << ", "
- << RC.SpillAlignment/8 << ", "
- << RC.CopyCost << ", "
- << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
- << ") {}\n";
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ const std::string &Name = RC.getName();
+
+ // Output the extern for the instance.
+ OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
}
-
- OS << "}\n";
+ OS << "} // end of namespace " << TargetName << "\n\n";
}
+ OS << "} // End llvm namespace\n";
+ OS << "#endif // GET_REGINFO_HEADER\n\n";
+}
- OS << "\nnamespace {\n";
- OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
- OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
- << "RegClass,\n";
- OS << " };\n";
+//
+// runTargetDesc - Output the target register and register file descriptions.
+//
+void
+RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank){
+ emitSourceFileHeader("Target Register and Register Classes Information", OS);
- // Emit register sub-registers / super-registers, aliases...
- std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
- std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
- std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
- std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
- typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
- DwarfRegNumsMapTy DwarfRegNums;
-
- const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- Record *R = Regs[i].TheDef;
- std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
- // Add information that R aliases all of the elements in the list... and
- // that everything in the list aliases R.
- for (unsigned j = 0, e = LI.size(); j != e; ++j) {
- Record *Reg = LI[j];
- if (RegisterAliases[R].count(Reg))
- errs() << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg)
- << " specified multiple times!\n";
- RegisterAliases[R].insert(Reg);
-
- if (RegisterAliases[Reg].count(R))
- errs() << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg)
- << " specified multiple times!\n";
- RegisterAliases[Reg].insert(R);
- }
- }
+ OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
+ OS << "#undef GET_REGINFO_TARGET_DESC\n";
- // Process sub-register sets.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- Record *R = Regs[i].TheDef;
- std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
- // Process sub-register set and add aliases information.
- for (unsigned j = 0, e = LI.size(); j != e; ++j) {
- Record *SubReg = LI[j];
- if (RegisterSubRegs[R].count(SubReg))
- errs() << "Warning: register " << getQualifiedName(SubReg)
- << " specified as a sub-register of " << getQualifiedName(R)
- << " multiple times!\n";
- addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
- RegisterAliases);
- }
+ OS << "namespace llvm {\n\n";
+
+ // Get access to MCRegisterClass data.
+ OS << "extern const MCRegisterClass " << Target.getName()
+ << "MCRegisterClasses[];\n";
+
+ // Start out by emitting each of the register classes.
+ const auto &RegisterClasses = RegBank.getRegClasses();
+ const auto &SubRegIndices = RegBank.getSubRegIndices();
+
+ // Collect all registers belonging to any allocatable class.
+ std::set<Record*> AllocatableRegs;
+
+ // Collect allocatable registers.
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ ArrayRef<Record*> Order = RC.getOrder();
+
+ if (RC.Allocatable)
+ AllocatableRegs.insert(Order.begin(), Order.end());
}
-
- // Print the SubregHashTable, a simple quadratically probed
- // hash table for determining if a register is a subregister
- // of another register.
- unsigned NumSubRegs = 0;
- std::map<Record*, unsigned> RegNo;
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- RegNo[Regs[i].TheDef] = i;
- NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
- }
-
- unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
- unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
- std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
-
- unsigned hashMisses = 0;
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- Record* R = Regs[i].TheDef;
- for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
- E = RegisterSubRegs[R].end(); I != E; ++I) {
- Record* RJ = *I;
- // We have to increase the indices of both registers by one when
- // computing the hash because, in the generated code, there
- // will be an extra empty slot at register 0.
- size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
- unsigned ProbeAmt = 2;
- while (SubregHashTable[index*2] != ~0U &&
- SubregHashTable[index*2+1] != ~0U) {
- index = (index + ProbeAmt) & (SubregHashTableSize-1);
- ProbeAmt += 2;
-
- hashMisses++;
- }
-
- SubregHashTable[index*2] = i;
- SubregHashTable[index*2+1] = RegNo[RJ];
- }
+
+ // Build a shared array of value types.
+ SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
+ for (const auto *RC : RegisterClasses)
+ VTSeqs.add(RC->VTs);
+ VTSeqs.layout();
+ OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
+ VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
+ OS << "};\n";
+
+ // Emit SubRegIndex names, skipping 0.
+ OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
+
+ for (const auto &Idx : SubRegIndices) {
+ OS << Idx.getName();
+ OS << "\", \"";
}
-
- OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
-
- if (SubregHashTableSize) {
- std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
-
- OS << " const unsigned SubregHashTable[] = { ";
- for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
- if (i != 0)
- // Insert spaces for nice formatting.
- OS << " ";
-
- if (SubregHashTable[2*i] != ~0U) {
- OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
- << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
- }
- }
-
- unsigned Idx = SubregHashTableSize*2-2;
- if (SubregHashTable[Idx] != ~0U) {
- OS << " "
- << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
- << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
- }
-
- OS << " const unsigned SubregHashTableSize = "
- << SubregHashTableSize << ";\n";
- } else {
- OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
- << " const unsigned SubregHashTableSize = 1;\n";
- }
-
- delete [] SubregHashTable;
-
-
- // Print the SuperregHashTable, a simple quadratically probed
- // hash table for determining if a register is a super-register
- // of another register.
- unsigned NumSupRegs = 0;
- RegNo.clear();
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- RegNo[Regs[i].TheDef] = i;
- NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
- }
-
- unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
- unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
- std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
-
- hashMisses = 0;
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- Record* R = Regs[i].TheDef;
- for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
- E = RegisterSuperRegs[R].end(); I != E; ++I) {
- Record* RJ = *I;
- // We have to increase the indices of both registers by one when
- // computing the hash because, in the generated code, there
- // will be an extra empty slot at register 0.
- size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
- unsigned ProbeAmt = 2;
- while (SuperregHashTable[index*2] != ~0U &&
- SuperregHashTable[index*2+1] != ~0U) {
- index = (index + ProbeAmt) & (SuperregHashTableSize-1);
- ProbeAmt += 2;
-
- hashMisses++;
- }
-
- SuperregHashTable[index*2] = i;
- SuperregHashTable[index*2+1] = RegNo[RJ];
- }
+ OS << "\" };\n\n";
+
+ // Emit SubRegIndex lane masks, including 0.
+ OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
+ for (const auto &Idx : SubRegIndices) {
+ OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
}
-
- OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
-
- if (SuperregHashTableSize) {
- std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
-
- OS << " const unsigned SuperregHashTable[] = { ";
- for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
- if (i != 0)
- // Insert spaces for nice formatting.
- OS << " ";
-
- if (SuperregHashTable[2*i] != ~0U) {
- OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
- << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+ OS << " };\n\n";
+
+ OS << "\n";
+
+ // Now that all of the structs have been emitted, emit the instances.
+ if (!RegisterClasses.empty()) {
+ OS << "\nstatic const TargetRegisterClass *const "
+ << "NullRegClasses[] = { nullptr };\n\n";
+
+ // Emit register class bit mask tables. The first bit mask emitted for a
+ // register class, RC, is the set of sub-classes, including RC itself.
+ //
+ // If RC has super-registers, also create a list of subreg indices and bit
+ // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
+ // SuperRC, that satisfies:
+ //
+ // For all SuperReg in SuperRC: SuperReg:Idx in RC
+ //
+ // The 0-terminated list of subreg indices starts at:
+ //
+ // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
+ //
+ // The corresponding bitmasks follow the sub-class mask in memory. Each
+ // mask has RCMaskWords uint32_t entries.
+ //
+ // Every bit mask present in the list has at least one bit set.
+
+ // Compress the sub-reg index lists.
+ typedef std::vector<const CodeGenSubRegIndex*> IdxList;
+ SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
+ SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
+ BitVector MaskBV(RegisterClasses.size());
+
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
+ printBitVectorAsHex(OS, RC.getSubClasses(), 32);
+
+ // Emit super-reg class masks for any relevant SubRegIndices that can
+ // project into RC.
+ IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
+ for (auto &Idx : SubRegIndices) {
+ MaskBV.reset();
+ RC.getSuperRegClasses(&Idx, MaskBV);
+ if (MaskBV.none())
+ continue;
+ SRIList.push_back(&Idx);
+ OS << "\n ";
+ printBitVectorAsHex(OS, MaskBV, 32);
+ OS << "// " << Idx.getName();
}
+ SuperRegIdxSeqs.add(SRIList);
+ OS << "\n};\n\n";
}
-
- unsigned Idx = SuperregHashTableSize*2-2;
- if (SuperregHashTable[Idx] != ~0U) {
- OS << " "
- << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
- << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
- }
-
- OS << " const unsigned SuperregHashTableSize = "
- << SuperregHashTableSize << ";\n";
- } else {
- OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
- << " const unsigned SuperregHashTableSize = 1;\n";
- }
-
- delete [] SuperregHashTable;
-
-
- // Print the AliasHashTable, a simple quadratically probed
- // hash table for determining if a register aliases another register.
- unsigned NumAliases = 0;
- RegNo.clear();
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- RegNo[Regs[i].TheDef] = i;
- NumAliases += RegisterAliases[Regs[i].TheDef].size();
- }
-
- unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
- unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
- std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
-
- hashMisses = 0;
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- Record* R = Regs[i].TheDef;
- for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
- E = RegisterAliases[R].end(); I != E; ++I) {
- Record* RJ = *I;
- // We have to increase the indices of both registers by one when
- // computing the hash because, in the generated code, there
- // will be an extra empty slot at register 0.
- size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
- unsigned ProbeAmt = 2;
- while (AliasesHashTable[index*2] != ~0U &&
- AliasesHashTable[index*2+1] != ~0U) {
- index = (index + ProbeAmt) & (AliasesHashTableSize-1);
- ProbeAmt += 2;
-
- hashMisses++;
- }
-
- AliasesHashTable[index*2] = i;
- AliasesHashTable[index*2+1] = RegNo[RJ];
+
+ OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
+ SuperRegIdxSeqs.layout();
+ SuperRegIdxSeqs.emit(OS, printSubRegIndex);
+ OS << "};\n\n";
+
+ // Emit NULL terminated super-class lists.
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
+
+ // Skip classes without supers. We can reuse NullRegClasses.
+ if (Supers.empty())
+ continue;
+
+ OS << "static const TargetRegisterClass *const "
+ << RC.getName() << "Superclasses[] = {\n";
+ for (const auto *Super : Supers)
+ OS << " &" << Super->getQualifiedName() << "RegClass,\n";
+ OS << " nullptr\n};\n\n";
}
- }
-
- OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
-
- if (AliasesHashTableSize) {
- std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
-
- OS << " const unsigned AliasesHashTable[] = { ";
- for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
- if (i != 0)
- // Insert spaces for nice formatting.
- OS << " ";
-
- if (AliasesHashTable[2*i] != ~0U) {
- OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
- << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+
+ // Emit methods.
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ if (!RC.AltOrderSelect.empty()) {
+ OS << "\nstatic inline unsigned " << RC.getName()
+ << "AltOrderSelect(const MachineFunction &MF) {"
+ << RC.AltOrderSelect << "}\n\n"
+ << "static ArrayRef<MCPhysReg> " << RC.getName()
+ << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
+ for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
+ ArrayRef<Record*> Elems = RC.getOrder(oi);
+ if (!Elems.empty()) {
+ OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
+ for (unsigned elem = 0; elem != Elems.size(); ++elem)
+ OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
+ OS << " };\n";
+ }
+ }
+ OS << " const MCRegisterClass &MCR = " << Target.getName()
+ << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
+ << " const ArrayRef<MCPhysReg> Order[] = {\n"
+ << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
+ for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
+ if (RC.getOrder(oi).empty())
+ OS << "),\n ArrayRef<MCPhysReg>(";
+ else
+ OS << "),\n makeArrayRef(AltOrder" << oi;
+ OS << ")\n };\n const unsigned Select = " << RC.getName()
+ << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
+ << ");\n return Order[Select];\n}\n";
}
}
-
- unsigned Idx = AliasesHashTableSize*2-2;
- if (AliasesHashTable[Idx] != ~0U) {
- OS << " "
- << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
- << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
- } else {
- OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
- }
-
- OS << " const unsigned AliasesHashTableSize = "
- << AliasesHashTableSize << ";\n";
- } else {
- OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
- << " const unsigned AliasesHashTableSize = 1;\n";
- }
-
- delete [] AliasesHashTable;
-
- if (!RegisterAliases.empty())
- OS << "\n\n // Register Alias Sets...\n";
-
- // Emit the empty alias list
- OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
- // Loop over all of the registers which have aliases, emitting the alias list
- // to memory.
- for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
- I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
- OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
- for (std::set<Record*>::iterator ASI = I->second.begin(),
- E = I->second.end(); ASI != E; ++ASI)
- OS << getQualifiedName(*ASI) << ", ";
- OS << "0 };\n";
- }
- if (!RegisterSubRegs.empty())
- OS << "\n\n // Register Sub-registers Sets...\n";
-
- // Emit the empty sub-registers list
- OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have sub-registers, emitting the
- // sub-registers list to memory.
- for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
- I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
- OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
- std::vector<Record*> SubRegsVector;
- for (std::set<Record*>::iterator ASI = I->second.begin(),
- E = I->second.end(); ASI != E; ++ASI)
- SubRegsVector.push_back(*ASI);
- RegisterSorter RS(RegisterSubRegs);
- std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
- for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
- OS << getQualifiedName(SubRegsVector[i]) << ", ";
- OS << "0 };\n";
- }
+ // Now emit the actual value-initialized register class instances.
+ OS << "\nnamespace " << RegisterClasses.front()->Namespace
+ << " { // Register class instances\n";
- if (!RegisterSuperRegs.empty())
- OS << "\n\n // Register Super-registers Sets...\n";
-
- // Emit the empty super-registers list
- OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have super-registers, emitting the
- // super-registers list to memory.
- for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
- I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
- OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
-
- std::vector<Record*> SuperRegsVector;
- for (std::set<Record*>::iterator ASI = I->second.begin(),
- E = I->second.end(); ASI != E; ++ASI)
- SuperRegsVector.push_back(*ASI);
- RegisterSorter RS(RegisterSubRegs);
- std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
- for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
- OS << getQualifiedName(SuperRegsVector[i]) << ", ";
- OS << "0 };\n";
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ OS << " extern const TargetRegisterClass " << RC.getName()
+ << "RegClass = {\n " << '&' << Target.getName()
+ << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
+ << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
+ << "SubClassMask,\n SuperRegIdxSeqs + "
+ << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
+ if (RC.getSuperClasses().empty())
+ OS << "NullRegClasses,\n ";
+ else
+ OS << RC.getName() << "Superclasses,\n ";
+ if (RC.AltOrderSelect.empty())
+ OS << "nullptr\n";
+ else
+ OS << RC.getName() << "GetRawAllocationOrder\n";
+ OS << " };\n\n";
+ }
+
+ OS << "}\n";
}
- OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
+ OS << "\nnamespace {\n";
+ OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
+ for (const auto *RC : RegisterClasses)
+ OS << " &" << RC->getQualifiedName() << "RegClass,\n";
+ OS << " };\n";
+ OS << "}\n"; // End of anonymous namespace...
- // Now that register alias and sub-registers sets have been emitted, emit the
- // register descriptors now.
- const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
- for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
- const CodeGenRegister &Reg = Registers[i];
- OS << " { \"";
- if (!Reg.TheDef->getValueAsString("AsmName").empty())
- OS << Reg.TheDef->getValueAsString("AsmName");
- else
- OS << Reg.getName();
- OS << "\",\t\"";
- OS << Reg.getName() << "\",\t";
- if (RegisterAliases.count(Reg.TheDef))
- OS << Reg.getName() << "_AliasSet,\t";
- else
- OS << "Empty_AliasSet,\t";
- if (RegisterSubRegs.count(Reg.TheDef))
- OS << Reg.getName() << "_SubRegsSet,\t";
- else
- OS << "Empty_SubRegsSet,\t";
- if (RegisterSuperRegs.count(Reg.TheDef))
- OS << Reg.getName() << "_SuperRegsSet },\n";
- else
- OS << "Empty_SuperRegsSet },\n";
+ // Emit extra information about registers.
+ const std::string &TargetName = Target.getName();
+ OS << "\nstatic const TargetRegisterInfoDesc "
+ << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
+ OS << " { 0, 0 },\n";
+
+ const auto &Regs = RegBank.getRegisters();
+ for (const auto &Reg : Regs) {
+ OS << " { ";
+ OS << Reg.CostPerUse << ", "
+ << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
}
- OS << " };\n"; // End of register descriptors...
- OS << "}\n\n"; // End of anonymous namespace...
+ OS << "};\n"; // End of register descriptors...
+
std::string ClassName = Target.getName() + "GenRegisterInfo";
- // Calculate the mapping of subregister+index pairs to physical registers.
- std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
- for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- int subRegIndex = SubRegs[i]->getValueAsInt("index");
- std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
- std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
-
- if (From.size() != To.size()) {
- errs() << "Error: register list and sub-register list not of equal length"
- << " in SubRegSet\n";
- exit(1);
+ auto SubRegIndicesSize =
+ std::distance(SubRegIndices.begin(), SubRegIndices.end());
+
+ if (!SubRegIndices.empty())
+ emitComposeSubRegIndices(OS, RegBank, ClassName);
+
+ // Emit getSubClassWithSubReg.
+ if (!SubRegIndices.empty()) {
+ OS << "const TargetRegisterClass *" << ClassName
+ << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
+ << " const {\n";
+ // Use the smallest type that can hold a regclass ID with room for a
+ // sentinel.
+ if (RegisterClasses.size() < UINT8_MAX)
+ OS << " static const uint8_t Table[";
+ else if (RegisterClasses.size() < UINT16_MAX)
+ OS << " static const uint16_t Table[";
+ else
+ PrintFatalError("Too many register classes.");
+ OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
+ for (const auto *RCP : RegisterClasses) {
+ const CodeGenRegisterClass &RC = *RCP;
+ OS << " {\t// " << RC.getName() << "\n";
+ for (auto &Idx : SubRegIndices) {
+ if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
+ OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
+ << " -> " << SRC->getName() << "\n";
+ else
+ OS << " 0,\t// " << Idx.getName() << "\n";
+ }
+ OS << " },\n";
}
-
- // For each entry in from/to vectors, insert the to register at index
- for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
- SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
- }
-
- // Emit the subregister + index mapping function based on the information
- // calculated above.
- OS << "unsigned " << ClassName
- << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
- << " switch (RegNo) {\n"
- << " default:\n return 0;\n";
- for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
- I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
- OS << " case " << getQualifiedName(I->first) << ":\n";
- OS << " switch (Index) {\n";
- OS << " default: return 0;\n";
- for (unsigned i = 0, e = I->second.size(); i != e; ++i)
- OS << " case " << (I->second)[i].first << ": return "
- << getQualifiedName((I->second)[i].second) << ";\n";
- OS << " };\n" << " break;\n";
+ OS << " };\n assert(RC && \"Missing regclass\");\n"
+ << " if (!Idx) return RC;\n --Idx;\n"
+ << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
+ << " unsigned TV = Table[RC->getID()][Idx];\n"
+ << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
}
- OS << " };\n";
- OS << " return 0;\n";
- OS << "}\n\n";
-
+
+ EmitRegUnitPressure(OS, RegBank, ClassName);
+
// Emit the constructor of the class...
- OS << ClassName << "::" << ClassName
- << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
- << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
- << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
- << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
- << " SubregHashTable, SubregHashTableSize,\n"
- << " SuperregHashTable, SuperregHashTableSize,\n"
- << " AliasesHashTable, AliasesHashTableSize) {\n"
- << "}\n\n";
+ OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
+ OS << "extern const char " << TargetName << "RegStrings[];\n";
+ OS << "extern const char " << TargetName << "RegClassStrings[];\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
+ OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
+ OS << "extern const MCRegisterInfo::SubRegCoveredBits "
+ << TargetName << "SubRegIdxRanges[];\n";
+ OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
+
+ EmitRegMappingTables(OS, Regs, true);
+
+ OS << ClassName << "::\n" << ClassName
+ << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
+ << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
+ << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
+ << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
+ OS.write_hex(RegBank.CoveringLanes);
+ OS << ") {\n"
+ << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
+ << ", RA, PC,\n " << TargetName
+ << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
+ << " " << TargetName << "RegUnitRoots,\n"
+ << " " << RegBank.getNumNativeRegUnits() << ",\n"
+ << " " << TargetName << "RegDiffLists,\n"
+ << " " << TargetName << "RegStrings,\n"
+ << " " << TargetName << "RegClassStrings,\n"
+ << " " << TargetName << "SubRegIdxLists,\n"
+ << " " << SubRegIndicesSize + 1 << ",\n"
+ << " " << TargetName << "SubRegIdxRanges,\n"
+ << " " << TargetName << "RegEncodingTable);\n\n";
+
+ EmitRegMapping(OS, Regs, true);
- // Collect all information about dwarf register numbers
+ OS << "}\n\n";
- // First, just pull all provided information to the map
- unsigned maxLength = 0;
- for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
- Record *Reg = Registers[i].TheDef;
- std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
- maxLength = std::max((size_t)maxLength, RegNums.size());
- if (DwarfRegNums.count(Reg))
- errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
- << "specified multiple times\n";
- DwarfRegNums[Reg] = RegNums;
- }
- // Now we know maximal length of number list. Append -1's, where needed
- for (DwarfRegNumsMapTy::iterator
- I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
- for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
- I->second.push_back(-1);
+ // Emit CalleeSavedRegs information.
+ std::vector<Record*> CSRSets =
+ Records.getAllDerivedDefinitions("CalleeSavedRegs");
+ for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
+ Record *CSRSet = CSRSets[i];
+ const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
+ assert(Regs && "Cannot expand CalleeSavedRegs instance");
- // Emit information about the dwarf register numbers.
- OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
- << "unsigned Flavour) const {\n"
- << " switch (Flavour) {\n"
- << " default:\n"
- << " assert(0 && \"Unknown DWARF flavour\");\n"
- << " return -1;\n";
-
- for (unsigned i = 0, e = maxLength; i != e; ++i) {
- OS << " case " << i << ":\n"
- << " switch (RegNum) {\n"
- << " default:\n"
- << " assert(0 && \"Invalid RegNum\");\n"
- << " return -1;\n";
-
- // Sort by name to get a stable order.
-
-
- for (DwarfRegNumsMapTy::iterator
- I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
- int RegNo = I->second[i];
- if (RegNo != -2)
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " return " << RegNo << ";\n";
- else
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " assert(0 && \"Invalid register for this mode\");\n"
- << " return -1;\n";
+ // Emit the *_SaveList list of callee-saved registers.
+ OS << "static const MCPhysReg " << CSRSet->getName()
+ << "_SaveList[] = { ";
+ for (unsigned r = 0, re = Regs->size(); r != re; ++r)
+ OS << getQualifiedName((*Regs)[r]) << ", ";
+ OS << "0 };\n";
+
+ // Emit the *_RegMask bit mask of call-preserved registers.
+ BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
+
+ // Check for an optional OtherPreserved set.
+ // Add those registers to RegMask, but not to SaveList.
+ if (DagInit *OPDag =
+ dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
+ SetTheory::RecSet OPSet;
+ RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
+ Covered |= RegBank.computeCoveredRegisters(
+ ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
}
- OS << " };\n";
+
+ OS << "static const uint32_t " << CSRSet->getName()
+ << "_RegMask[] = { ";
+ printBitVectorAsHex(OS, Covered, 32);
+ OS << "};\n";
}
-
- OS << " };\n}\n\n";
+ OS << "\n\n";
- OS << "} // End llvm namespace \n";
+ OS << "} // End llvm namespace\n";
+ OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
+}
+
+void RegisterInfoEmitter::run(raw_ostream &OS) {
+ CodeGenTarget Target(Records);
+ CodeGenRegBank &RegBank = Target.getRegBank();
+ RegBank.computeDerivedInfo();
+
+ runEnums(OS, Target, RegBank);
+ runMCDesc(OS, Target, RegBank);
+ runTargetHeader(OS, Target, RegBank);
+ runTargetDesc(OS, Target, RegBank);
}
+
+namespace llvm {
+
+void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
+ RegisterInfoEmitter(RK).run(OS);
+}
+
+} // End llvm namespace
projects / oota-llvm.git / blobdiff