//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting a description of a target
#include "Record.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/Streams.h"
#include <set>
using namespace llvm;
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
-
+ OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
OS << " };\n";
if (!Namespace.empty())
OS << "}\n";
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
- OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
+ OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
+ OS << "#include <string>\n\n";
OS << "namespace llvm {\n\n";
OS << "struct " << ClassName << " : public MRegisterInfo {\n"
<< " " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
- << " const unsigned* getCalleeSaveRegs() const;\n"
+ << " virtual int getDwarfRegNumFull(unsigned RegNum, "
+ << "unsigned Flavour) const;\n"
+ << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
+ << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
<< "};\n\n";
- std::vector<Record*> RegisterClasses =
- Records.getAllDerivedDefinitions("RegisterClass");
+ const std::vector<CodeGenRegisterClass> &RegisterClasses =
+ Target.getRegisterClasses();
- OS << "namespace " << TargetName << " { // Register classes\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- const std::string &Name = RegisterClasses[i]->getName();
- if (Name.size() < 9 || Name[9] != '.') // Ignore anonymous classes
- OS << " extern TargetRegisterClass *" << Name << "RegisterClass;\n";
+ if (!RegisterClasses.empty()) {
+ OS << "namespace " << RegisterClasses[0].Namespace
+ << " { // Register classes\n";
+
+ OS << " enum {\n";
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ if (i) OS << ",\n";
+ OS << " " << RegisterClasses[i].getName() << "RegClassID";
+ if (!i) OS << " = 1";
+ }
+ OS << "\n };\n\n";
+
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ const std::string &Name = RegisterClasses[i].getName();
+
+ // Output the register class definition.
+ OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
+ << " " << Name << "Class();\n"
+ << RegisterClasses[i].MethodProtos << " };\n";
+
+ // Output the extern for the instance.
+ OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
+ // Output the extern for the pointer to the instance (should remove).
+ OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
+ << Name << "RegClass;\n";
+ }
+ OS << "} // end of namespace " << TargetName << "\n\n";
}
- OS << "} // end of namespace " << TargetName << "\n\n";
OS << "} // End llvm namespace \n";
}
+bool isSubRegisterClass(const CodeGenRegisterClass &RC,
+ std::set<Record*> &RegSet) {
+ for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
+ Record *Reg = RC.Elements[i];
+ if (!RegSet.count(Reg))
+ return false;
+ }
+ return true;
+}
+
+static void addSuperReg(Record *R, Record *S,
+ std::map<Record*, std::set<Record*> > &SubRegs,
+ std::map<Record*, std::set<Record*> > &SuperRegs,
+ std::map<Record*, std::set<Record*> > &Aliases,
+ RegisterInfoEmitter &RIE) {
+ if (R == S) {
+ cerr << "Error: recursive sub-register relationship between"
+ << " register " << RIE.getQualifiedName(R)
+ << " and its sub-registers?\n";
+ abort();
+ }
+ if (!SuperRegs[R].insert(S).second)
+ return;
+ SubRegs[S].insert(R);
+ Aliases[R].insert(S);
+ Aliases[S].insert(R);
+ if (SuperRegs.count(S))
+ for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
+ E = SuperRegs[S].end(); I != E; ++I)
+ addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
+}
+
+static void addSubSuperReg(Record *R, Record *S,
+ std::map<Record*, std::set<Record*> > &SubRegs,
+ std::map<Record*, std::set<Record*> > &SuperRegs,
+ std::map<Record*, std::set<Record*> > &Aliases,
+ RegisterInfoEmitter &RIE) {
+ if (R == S) {
+ cerr << "Error: recursive sub-register relationship between"
+ << " register " << RIE.getQualifiedName(R)
+ << " and its sub-registers?\n";
+ abort();
+ }
+
+ if (!SubRegs[R].insert(S).second)
+ return;
+ addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
+ Aliases[R].insert(S);
+ Aliases[S].insert(R);
+ if (SubRegs.count(S))
+ for (std::set<Record*>::iterator I = SubRegs[S].begin(),
+ E = SubRegs[S].end(); I != E; ++I)
+ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
+}
+
// RegisterInfoEmitter::run - Main register file description emitter.
//
void RegisterInfoEmitter::run(std::ostream &OS) {
const std::vector<CodeGenRegisterClass> &RegisterClasses =
Target.getRegisterClasses();
- std::set<Record*> RegistersFound;
- std::vector<std::string> RegClassNames;
-
// Loop over all of the register classes... emitting each one.
OS << "namespace { // Register classes...\n";
// belongs to.
std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
+ // Emit the register enum value arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
- std::string Name = RC.getName();
- if (Name.size() > 9 && Name[9] == '.') {
- static unsigned AnonCounter = 0;
- Name = "AnonRegClass_"+utostr(AnonCounter++);
- }
-
- RegClassNames.push_back(Name);
-
- // Emit the register list now...
- OS << " // " << Name << " Register Class...\n const unsigned " << Name
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ // Emit the register list now.
+ OS << " // " << Name << " Register Class...\n"
+ << " static const unsigned " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
Record *Reg = RC.Elements[i];
- if (RegistersFound.count(Reg))
- throw "Register '" + Reg->getName() +
- "' included in multiple register classes!";
- RegistersFound.insert(Reg);
OS << getQualifiedName(Reg) << ", ";
// Keep track of which regclasses this register is in.
RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
}
OS << "\n };\n\n";
+ }
+
+ // Emit the ValueType arrays for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName() + "VTs";
+
+ // Emit the register list now.
+ OS << " // " << Name
+ << " Register Class Value Types...\n"
+ << " static const MVT::ValueType " << Name
+ << "[] = {\n ";
+ for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
+ OS << getEnumName(RC.VTs[i]) << ", ";
+ OS << "MVT::Other\n };\n\n";
+ }
+ OS << "} // end anonymous namespace\n\n";
+
+ // Now that all of the structs have been emitted, emit the instances.
+ if (!RegisterClasses.empty()) {
+ OS << "namespace " << RegisterClasses[0].Namespace
+ << " { // Register class instances\n";
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
+ OS << " " << RegisterClasses[i].getName() << "Class\t"
+ << RegisterClasses[i].getName() << "RegClass;\n";
+
+ std::map<unsigned, std::set<unsigned> > SuperClassMap;
+ std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
+ OS << "\n";
+
+ // Emit the sub-register classes for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Sub-register Classess...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SubRegClasses [] = {\n ";
+
+ bool Empty = true;
+
+ for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
+ subrc != subrcMax; ++subrc) {
+ unsigned rc2 = 0, e2 = RegisterClasses.size();
+ for (; rc2 != e2; ++rc2) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+ if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+
+ std::map<unsigned, std::set<unsigned> >::iterator SCMI =
+ SuperRegClassMap.find(rc2);
+ if (SCMI == SuperRegClassMap.end()) {
+ SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
+ SCMI = SuperRegClassMap.find(rc2);
+ }
+ SCMI->second.insert(rc);
+ break;
+ }
+ }
+ if (rc2 == e2)
+ throw "Register Class member '" +
+ RC.SubRegClasses[subrc]->getName() +
+ "' is not a valid RegisterClass!";
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
+ // Emit the super-register classes for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Super-register Classess...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SuperRegClasses [] = {\n ";
+
+ bool Empty = true;
+ std::map<unsigned, std::set<unsigned> >::iterator I =
+ SuperRegClassMap.find(rc);
+ if (I != SuperRegClassMap.end()) {
+ for (std::set<unsigned>::iterator II = I->second.begin(),
+ EE = I->second.end(); II != EE; ++II) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+ }
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
+ // Emit the sub-classes array for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ std::set<Record*> RegSet;
+ for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
+ Record *Reg = RC.Elements[i];
+ RegSet.insert(Reg);
+ }
+
+ OS << " // " << Name
+ << " Register Class sub-classes...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "Subclasses [] = {\n ";
+
+ bool Empty = true;
+ for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+ if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
+ RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
+ continue;
+
+ if (!Empty) OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+
+ std::map<unsigned, std::set<unsigned> >::iterator SCMI =
+ SuperClassMap.find(rc2);
+ if (SCMI == SuperClassMap.end()) {
+ SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
+ SCMI = SuperClassMap.find(rc2);
+ }
+ SCMI->second.insert(rc);
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
- OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
- << " " << Name << "Class() : TargetRegisterClass("
- << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
- << Name << " + " << RC.Elements.size() << ") {}\n"
- << RC.MethodDefinitions << " } " << Name << "Instance;\n\n";
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Register Class super-classes...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "Superclasses [] = {\n ";
+
+ bool Empty = true;
+ std::map<unsigned, std::set<unsigned> >::iterator I =
+ SuperClassMap.find(rc);
+ if (I != SuperClassMap.end()) {
+ for (std::set<unsigned>::iterator II = I->second.begin(),
+ EE = I->second.end(); II != EE; ++II) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
+ if (!Empty) OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+ }
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
+
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ const CodeGenRegisterClass &RC = RegisterClasses[i];
+ OS << RC.MethodBodies << "\n";
+ OS << RC.getName() << "Class::" << RC.getName()
+ << "Class() : TargetRegisterClass("
+ << RC.getName() + "RegClassID" << ", "
+ << RC.getName() + "VTs" << ", "
+ << RC.getName() + "Subclasses" << ", "
+ << RC.getName() + "Superclasses" << ", "
+ << RC.getName() + "SubRegClasses" << ", "
+ << RC.getName() + "SuperRegClasses" << ", "
+ << RC.SpillSize/8 << ", "
+ << RC.SpillAlignment/8 << ", "
+ << RC.CopyCost << ", "
+ << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
+ << ") {}\n";
+ }
+
+ OS << "}\n";
}
+ OS << "\nnamespace {\n";
OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
- for (unsigned i = 0, e = RegClassNames.size(); i != e; ++i)
- OS << " &" << RegClassNames[i] << "Instance,\n";
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
+ OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
+ << "RegClass,\n";
OS << " };\n";
- // Emit register class aliases...
- std::vector<Record*> RegisterAliasesRecs =
- Records.getAllDerivedDefinitions("RegisterAliases");
+ // Emit register sub-registers / super-registers, aliases...
+ std::map<Record*, std::set<Record*> > RegisterImmSubRegs;
+ std::map<Record*, std::set<Record*> > RegisterSubRegs;
+ std::map<Record*, std::set<Record*> > RegisterSuperRegs;
std::map<Record*, std::set<Record*> > RegisterAliases;
+ std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
+ std::map<Record*, std::vector<int> > DwarfRegNums;
+
+ const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
- for (unsigned i = 0, e = RegisterAliasesRecs.size(); i != e; ++i) {
- Record *AS = RegisterAliasesRecs[i];
- Record *R = AS->getValueAsDef("Reg");
- ListInit *LI = AS->getValueAsListInit("Aliases");
-
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record *R = Regs[i].TheDef;
+ std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
// Add information that R aliases all of the elements in the list... and
// that everything in the list aliases R.
- for (unsigned j = 0, e = LI->getSize(); j != e; ++j) {
- DefInit *Reg = dynamic_cast<DefInit*>(LI->getElement(j));
- if (!Reg) throw "ERROR: Alias list element is not a def!";
- if (RegisterAliases[R].count(Reg->getDef()))
- std::cerr << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg->getDef())
- << " specified multiple times!\n";
- RegisterAliases[R].insert(Reg->getDef());
-
- if (RegisterAliases[Reg->getDef()].count(R))
- std::cerr << "Warning: register alias between " << getQualifiedName(R)
- << " and " << getQualifiedName(Reg->getDef())
- << " specified multiple times!\n";
- RegisterAliases[Reg->getDef()].insert(R);
+ for (unsigned j = 0, e = LI.size(); j != e; ++j) {
+ Record *Reg = LI[j];
+ if (RegisterAliases[R].count(Reg))
+ cerr << "Warning: register alias between " << getQualifiedName(R)
+ << " and " << getQualifiedName(Reg)
+ << " specified multiple times!\n";
+ RegisterAliases[R].insert(Reg);
+
+ if (RegisterAliases[Reg].count(R))
+ cerr << "Warning: register alias between " << getQualifiedName(R)
+ << " and " << getQualifiedName(Reg)
+ << " specified multiple times!\n";
+ RegisterAliases[Reg].insert(R);
+ }
+ }
+
+ // Process sub-register sets.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record *R = Regs[i].TheDef;
+ std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
+ // Process sub-register set and add aliases information.
+ for (unsigned j = 0, e = LI.size(); j != e; ++j) {
+ Record *SubReg = LI[j];
+ if (RegisterSubRegs[R].count(SubReg))
+ cerr << "Warning: register " << getQualifiedName(SubReg)
+ << " specified as a sub-register of " << getQualifiedName(R)
+ << " multiple times!\n";
+ RegisterImmSubRegs[R].insert(SubReg);
+ addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
+ RegisterAliases, *this);
}
}
if (!RegisterAliases.empty())
OS << "\n\n // Register Alias Sets...\n";
-
+
// Emit the empty alias list
OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
// Loop over all of the registers which have aliases, emitting the alias list
OS << "0 };\n";
}
- OS << "\n const MRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t\t0,\t0 },\n";
+ if (!RegisterSubRegs.empty())
+ OS << "\n\n // Register Sub-registers Sets...\n";
+
+ // Emit the empty sub-registers list
+ OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (std::map<Record*, std::set<Record*> >::iterator
+ I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
+ OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
+ for (std::set<Record*>::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+ OS << "0 };\n";
+ }
+
+ if (!RegisterImmSubRegs.empty())
+ OS << "\n\n // Register Immediate Sub-registers Sets...\n";
+
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (std::map<Record*, std::set<Record*> >::iterator
+ I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end();
+ I != E; ++I) {
+ OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { ";
+ for (std::set<Record*>::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+ OS << "0 };\n";
+ }
+
+ if (!RegisterSuperRegs.empty())
+ OS << "\n\n // Register Super-registers Sets...\n";
+
+ // Emit the empty super-registers list
+ OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have super-registers, emitting the
+ // super-registers list to memory.
+ for (std::map<Record*, std::set<Record*> >::iterator
+ I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
+ OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
+ for (std::set<Record*>::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+ OS << "0 };\n";
+ }
+ OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
- // Now that register alias sets have been emitted, emit the register
- // descriptors now.
+ // Now that register alias and sub-registers sets have been emitted, emit the
+ // register descriptors now.
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
OS << Reg.getName() << "_AliasSet,\t";
else
OS << "Empty_AliasSet,\t";
-
- // Figure out what the size and alignment of the spill slots are for this
- // reg. This may be explicitly declared in the register, or it may be
- // inferred from the register classes it is part of.
- std::multimap<Record*, const CodeGenRegisterClass*>::iterator I, E;
- tie(I, E) = RegClassesBelongedTo.equal_range(Reg.TheDef);
- unsigned SpillSize = Reg.DeclaredSpillSize;
- unsigned SpillAlign = Reg.DeclaredSpillAlignment;
- for (; I != E; ++I) { // For each reg class this belongs to.
- const CodeGenRegisterClass *RC = I->second;
- if (SpillSize == 0)
- SpillSize = RC->SpillSize;
- else if (SpillSize != RC->SpillSize)
- throw "Spill size for regclass '" + RC->getName() +
- "' doesn't match spill sized already inferred for register '" +
- Reg.getName() + "'!";
- if (SpillAlign == 0)
- SpillAlign = RC->SpillAlignment;
- else if (SpillAlign != RC->SpillAlignment)
- throw "Spill alignment for regclass '" + RC->getName() +
- "' doesn't match spill sized already inferred for register '" +
- Reg.getName() + "'!";
- }
-
- OS << SpillSize << ", " << SpillAlign << " },\n";
+ if (RegisterSubRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_SubRegsSet,\t";
+ else
+ OS << "Empty_SubRegsSet,\t";
+ if (RegisterImmSubRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_ImmSubRegsSet,\t";
+ else
+ OS << "Empty_SubRegsSet,\t";
+ if (RegisterSuperRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_SuperRegsSet },\n";
+ else
+ OS << "Empty_SuperRegsSet },\n";
}
OS << " };\n"; // End of register descriptors...
OS << "}\n\n"; // End of anonymous namespace...
- OS << "namespace " << Target.getName() << " { // Register classes\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- const std::string &Name = RegisterClasses[i].getName();
- if (Name.size() < 9 || Name[9] != '.') // Ignore anonymous classes
- OS << " TargetRegisterClass *" << Name << "RegisterClass = &"
- << Name << "Instance;\n";
- }
- OS << "} // end of namespace " << Target.getName() << "\n\n";
-
-
-
std::string ClassName = Target.getName() + "GenRegisterInfo";
+
+ // Calculate the mapping of subregister+index pairs to physical registers.
+ std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
+ for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
+ int subRegIndex = SubRegs[i]->getValueAsInt("index");
+ std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
+ std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
+
+ if (From.size() != To.size()) {
+ cerr << "Error: register list and sub-register list not of equal length"
+ << " in SubRegSet\n";
+ exit(1);
+ }
+
+ // For each entry in from/to vectors, insert the to register at index
+ for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
+ SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
+ }
+
+ // Emit the subregister + index mapping function based on the information
+ // calculated above.
+ OS << "unsigned " << ClassName
+ << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
+ << " switch (RegNo) {\n"
+ << " default: abort(); break;\n";
+ for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
+ I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+ OS << " case " << getQualifiedName(I->first) << ":\n";
+ OS << " switch (Index) {\n";
+ OS << " default: abort(); break;\n";
+ for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << " case " << (I->second)[i].first << ": return "
+ << getQualifiedName((I->second)[i].second) << ";\n";
+ OS << " }; break;\n";
+ }
+ OS << " };\n";
+ OS << " return 0;\n";
+ OS << "}\n\n";
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
- << ", RegisterClasses, RegisterClasses+" << RegClassNames.size() << ",\n "
+ << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
+
+ // Collect all information about dwarf register numbers
+
+ // First, just pull all provided information to the map
+ unsigned maxLength = 0;
+ for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+ Record *Reg = Registers[i].TheDef;
+ std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
+ maxLength = std::max((size_t)maxLength, RegNums.size());
+ if (DwarfRegNums.count(Reg))
+ cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
+ << "specified multiple times\n";
+ DwarfRegNums[Reg] = RegNums;
+ }
+
+ // Now we know maximal length of number list. Append -1's, where needed
+ for (std::map<Record*, std::vector<int> >::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
+ for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
+ I->second.push_back(-1);
+
+ // Emit information about the dwarf register numbers.
+ OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
+ << "unsigned Flavour) const {\n"
+ << " switch (Flavour) {\n"
+ << " default:\n"
+ << " assert(0 && \"Unknown DWARF flavour\");\n"
+ << " return -1;\n";
- // Emit the getCalleeSaveRegs method...
- OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n"
- << " static const unsigned CalleeSaveRegs[] = {\n ";
-
- const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters();
- for (unsigned i = 0, e = CSR.size(); i != e; ++i)
- OS << getQualifiedName(CSR[i]) << ", ";
- OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n";
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << " case " << i << ":\n"
+ << " switch (RegNum) {\n"
+ << " default:\n"
+ << " assert(0 && \"Invalid RegNum\");\n"
+ << " return -1;\n";
+
+ for (std::map<Record*, std::vector<int> >::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
+ int RegNo = I->second[i];
+ if (RegNo != -2)
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " return " << RegNo << ";\n";
+ else
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " assert(0 && \"Invalid register for this mode\");\n"
+ << " return -1;\n";
+ }
+ OS << " };\n";
+ }
+
+ OS << " };\n}\n\n";
+
OS << "} // End llvm namespace \n";
}