OS << "}\n";
}
+ ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
+ if (!SubRegIndices.empty()) {
+ OS << "\n// Subregister indices\n";
+ std::string Namespace =
+ SubRegIndices[0]->getNamespace();
+ if (!Namespace.empty())
+ OS << "namespace " << Namespace << " {\n";
+ OS << "enum {\n NoSubRegister,\n";
+ for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
+ OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
+ OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
+ if (!Namespace.empty())
+ OS << "}\n";
+ }
OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_ENUM\n\n";
const std::string &TargetName = Target.getName();
- OS << "\nnamespace {\n";
-
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
+ OS << "extern const uint16_t " << TargetName << "RegOverlaps[] = {\n";
+
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
- OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
+ OS << " /* " << Reg->getName() << "_Overlaps */ "
<< getQualifiedName(Reg->TheDef) << ", ";
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
I != E; ++I)
if (*I != Reg)
OS << getQualifiedName((*I)->TheDef) << ", ";
- OS << "0 };\n";
+ OS << "0,\n";
}
+ OS << "};\n\n";
+ OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n";
// Emit the empty sub-registers list
- OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
+ OS << " /* Empty_SubRegsSet */ 0,\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
// getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR, RegBank);
- OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
+ OS << " /* " << Reg.getName() << "_SubRegsSet */ ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
+ OS << "0,\n";
}
+ OS << "};\n\n";
+ OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n";
// Emit the empty super-registers list
- OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+ OS << " /* Empty_SuperRegsSet */ 0,\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
- OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
+ OS << " /* " << Reg.getName() << "_SuperRegsSet */ ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
+ OS << "0,\n";
}
- OS << "}\n"; // End of anonymous namespace...
+ OS << "};\n\n";
- OS << "\nextern const MCRegisterDesc " << TargetName
+ OS << "extern const MCRegisterDesc " << TargetName
<< "RegDesc[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\", 0, 0, 0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
+ unsigned OverlapsIndex = 0;
+ unsigned SubRegIndex = 1; // skip 1 for empty set
+ unsigned SuperRegIndex = 1; // skip 1 for empty set
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
+ const CodeGenRegister *Reg = Regs[i];
OS << " { \"";
- OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
- if (!Reg.getSubRegs().empty())
- OS << Reg.getName() << "_SubRegsSet,\t";
- else
- OS << "Empty_SubRegsSet,\t";
- if (!Reg.getSuperRegs().empty())
- OS << Reg.getName() << "_SuperRegsSet";
- else
- OS << "Empty_SuperRegsSet";
+ OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
+ << OverlapsIndex << ", ";
+ OverlapsIndex += Overlaps[Reg].size() + 1;
+ if (!Reg->getSubRegs().empty()) {
+ OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
+ << ", ";
+ // FIXME not very nice to recalculate this
+ SetVector<CodeGenRegister*> SR;
+ Reg->addSubRegsPreOrder(SR, RegBank);
+ SubRegIndex += SR.size() + 1;
+ } else
+ OS << "/* Empty_SubRegsSet */ 0, ";
+ if (!Reg->getSuperRegs().empty()) {
+ OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
+ SuperRegIndex += Reg->getSuperRegs().size() + 1;
+ } else
+ OS << "/* Empty_SuperRegsSet */ 0";
OS << " },\n";
}
OS << "};\n\n"; // End of register descriptors...
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
- << " static const unsigned " << Name
+ << " const uint16_t " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
Record *Reg = Order[i];
OS << "\n };\n\n";
OS << " // " << Name << " Bit set.\n"
- << " static const unsigned char " << Name
+ << " const uint8_t " << Name
<< "Bits[] = {\n ";
BitVectorEmitter BVE;
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
<< RC.Allocatable << ", "
- << RC.getName() << ", " << RC.getName() << " + "
- << RC.getOrder().size() << ", "
- << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
- << " },\n";
+ << RC.getName() << ", " << RC.getName() << "Bits, "
+ << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
}
OS << "};\n\n";
+ // Emit the data table for getSubReg().
+ ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
+ if (SubRegIndices.size()) {
+ OS << "const uint16_t " << TargetName << "SubRegTable[]["
+ << SubRegIndices.size() << "] = {\n";
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
+ OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
+ if (SRM.empty()) {
+ OS << " {0},\n";
+ continue;
+ }
+ OS << " {";
+ for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
+ // FIXME: We really should keep this to 80 columns...
+ CodeGenRegister::SubRegMap::const_iterator SubReg =
+ SRM.find(SubRegIndices[j]);
+ if (SubReg != SRM.end())
+ OS << getQualifiedName(SubReg->second->TheDef);
+ else
+ OS << "0";
+ if (j != je - 1)
+ OS << ", ";
+ }
+ OS << "}" << (i != e ? "," : "") << "\n";
+ }
+ OS << "};\n\n";
+ OS << "const uint16_t *get" << TargetName
+ << "SubRegTable() {\n return (const uint16_t *)" << TargetName
+ << "SubRegTable;\n}\n\n";
+ }
+
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
- << RegisterClasses.size() << ");\n\n";
+ << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
+ << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet, ";
+ if (SubRegIndices.size() != 0)
+ OS << "(uint16_t*)" << TargetName << "SubRegTable, "
+ << SubRegIndices.size() << ");\n\n";
+ else
+ OS << "NULL, 0);\n\n";
EmitRegMapping(OS, Regs, false);
OS << "}\n\n";
-
OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
}
<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n"
- << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
- << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
<< " const TargetRegisterClass *"
"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
"unsigned) const;\n"
<< "};\n\n";
- ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
- if (!SubRegIndices.empty()) {
- OS << "\n// Subregister indices\n";
- std::string Namespace =
- SubRegIndices[0]->getNamespace();
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << "enum {\n NoSubRegister,\n";
- for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
- OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
- OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
- if (!Namespace.empty())
- OS << "}\n";
- }
-
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
if (!RegisterClasses.empty()) {
const CodeGenRegisterClass &RC = *RegisterClasses[i];
const std::string &Name = RC.getName();
- // Output the register class definition.
- OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
- << " " << Name << "Class();\n";
- if (!RC.AltOrderSelect.empty())
- OS << " ArrayRef<unsigned> "
- "getRawAllocationOrder(const MachineFunction&) const;\n";
- OS << " };\n";
-
// Output the extern for the instance.
- OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
+ OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
// Output the extern for the pointer to the instance (should remove).
- OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
- << Name << "RegClass;\n";
+ OS << " static const TargetRegisterClass * const " << Name
+ << "RegisterClass = &" << Name << "RegClass;\n";
}
OS << "} // end of namespace " << TargetName << "\n\n";
}
// Emit the register list now.
OS << " // " << Name
<< " Register Class Value Types...\n"
- << " static const MVT::SimpleValueType " << Name
+ << " const MVT::SimpleValueType " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";
// Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) {
- OS << "namespace " << RegisterClasses[0]->Namespace
- << " { // Register class instances\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
- OS << " " << RegisterClasses[i]->getName() << "Class\t"
- << RegisterClasses[i]->getName() << "RegClass;\n";
-
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
- OS << "\n static const TargetRegisterClass* const "
- << "NullRegClasses[] = { NULL };\n\n";
+ OS << "\nstatic const TargetRegisterClass *const "
+ << "NullRegClasses[] = { NULL };\n\n";
unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.getName();
- OS << " // " << Name
+ OS << "// " << Name
<< " Super-register Classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "SuperRegClasses[] = {\n ";
+ << "static const TargetRegisterClass *const "
+ << Name << "SuperRegClasses[] = {\n ";
bool Empty = true;
std::map<unsigned, std::set<unsigned> >::iterator I =
}
OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
+ OS << "\n};\n\n";
}
}
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.getName();
- OS << " static const unsigned " << Name << "SubclassMask[] = { ";
+ OS << "static const unsigned " << Name << "SubclassMask[] = {\n ";
printBitVectorAsHex(OS, RC.getSubClasses(), 32);
- OS << "};\n\n";
+ OS << "\n};\n\n";
}
// Emit NULL terminated super-class lists.
if (Supers.empty())
continue;
- OS << " static const TargetRegisterClass* const "
+ OS << "static const TargetRegisterClass *const "
<< RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i)
- OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
- OS << " NULL\n };\n\n";
+ OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
+ OS << " NULL\n};\n\n";
}
// Emit methods.
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = *RegisterClasses[i];
- OS << RC.getName() << "Class::" << RC.getName()
- << "Class() : TargetRegisterClass(&"
- << Target.getName() << "MCRegisterClasses["
- << RC.getName() + "RegClassID" << "], "
- << RC.getName() + "VTs" << ", "
- << RC.getName() + "SubclassMask" << ", ";
- if (RC.getSuperClasses().empty())
- OS << "NullRegClasses, ";
- else
- OS << RC.getName() + "Superclasses, ";
- OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
- << "RegClasses"
- << ") {}\n";
if (!RC.AltOrderSelect.empty()) {
OS << "\nstatic inline unsigned " << RC.getName()
<< "AltOrderSelect(const MachineFunction &MF) {"
- << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
- << RC.getName() << "Class::"
- << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
+ << RC.AltOrderSelect << "}\n\n"
+ << "static ArrayRef<uint16_t> " << RC.getName()
+ << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
ArrayRef<Record*> Elems = RC.getOrder(oi);
if (!Elems.empty()) {
- OS << " static const unsigned AltOrder" << oi << "[] = {";
+ OS << " static const uint16_t AltOrder" << oi << "[] = {";
for (unsigned elem = 0; elem != Elems.size(); ++elem)
OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
OS << " };\n";
}
OS << " const MCRegisterClass &MCR = " << Target.getName()
<< "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
- << " static const ArrayRef<unsigned> Order[] = {\n"
+ << " const ArrayRef<uint16_t> Order[] = {\n"
<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
if (RC.getOrder(oi).empty())
- OS << "),\n ArrayRef<unsigned>(";
+ OS << "),\n ArrayRef<uint16_t>(";
else
OS << "),\n makeArrayRef(AltOrder" << oi;
OS << ")\n };\n const unsigned Select = " << RC.getName()
}
}
+ // Now emit the actual value-initialized register class instances.
+ OS << "namespace " << RegisterClasses[0]->Namespace
+ << " { // Register class instances\n";
+
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ const CodeGenRegisterClass &RC = *RegisterClasses[i];
+ OS << " extern const TargetRegisterClass "
+ << RegisterClasses[i]->getName() << "RegClass = {\n "
+ << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
+ << "RegClassID],\n "
+ << RC.getName() << "VTs,\n "
+ << RC.getName() << "SubclassMask,\n ";
+ if (RC.getSuperClasses().empty())
+ OS << "NullRegClasses,\n ";
+ else
+ OS << RC.getName() << "Superclasses,\n ";
+ OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
+ << "RegClasses,\n ";
+ if (RC.AltOrderSelect.empty())
+ OS << "0\n";
+ else
+ OS << RC.getName() << "GetRawAllocationOrder\n";
+ OS << " };\n\n";
+ }
+
OS << "}\n";
}
// Calculate the mapping of subregister+index pairs to physical registers.
- // This will also create further anonymous indexes.
+ // This will also create further anonymous indices.
unsigned NamedIndices = RegBank.getNumNamedIndices();
// Emit SubRegIndex names, skipping 0
}
OS << "\" };\n\n";
- // Emit names of the anonymus subreg indexes.
+ // Emit names of the anonymous subreg indices.
if (SubRegIndices.size() > NamedIndices) {
OS << " enum {";
for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
std::string ClassName = Target.getName() + "GenRegisterInfo";
- // Emit the subregister + index mapping function based on the information
- // calculated above.
- OS << "unsigned " << ClassName
- << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
- << " switch (RegNo) {\n"
- << " default:\n return 0;\n";
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
- if (SRM.empty())
- continue;
- OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
- OS << " switch (Index) {\n";
- OS << " default: return 0;\n";
- for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
- ie = SRM.end(); ii != ie; ++ii)
- OS << " case " << ii->first->getQualifiedName()
- << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
- OS << " };\n" << " break;\n";
- }
- OS << " };\n";
- OS << " return 0;\n";
- OS << "}\n\n";
-
- OS << "unsigned " << ClassName
- << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
- << " switch (RegNo) {\n"
- << " default:\n return 0;\n";
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
- if (SRM.empty())
- continue;
- OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
- for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
- ie = SRM.end(); ii != ie; ++ii)
- OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
- << ") return " << ii->first->getQualifiedName() << ";\n";
- OS << " return 0;\n";
- }
- OS << " };\n";
- OS << " return 0;\n";
- OS << "}\n\n";
-
// Emit composeSubRegIndices
OS << "unsigned " << ClassName
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
const unsigned BVWords = (RegisterClasses.size()+31)/32;
BitVector BV(RegisterClasses.size());
- OS << " static const unsigned Table[" << RegisterClasses.size()
+ OS << " static const uint32_t Table[" << RegisterClasses.size()
<< "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
// Emit the constructor of the class...
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
-
- OS << ClassName << "::" << ClassName
+ OS << "extern const uint16_t " << TargetName << "RegOverlaps[];\n";
+ OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n";
+ OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n";
+ if (SubRegIndices.size() != 0)
+ OS << "extern const uint16_t *get" << TargetName
+ << "SubRegTable();\n";
+
+ OS << ClassName << "::\n" << ClassName
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
- << " " << TargetName << "SubRegIndexTable) {\n"
+ << " " << TargetName << "SubRegIndexTable) {\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
- << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
- << RegisterClasses.size() << ");\n\n";
+ << Regs.size()+1 << ", RA,\n " << TargetName
+ << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
+ << " " << TargetName << "RegOverlaps, "
+ << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet,\n"
+ << " ";
+ if (SubRegIndices.size() != 0)
+ OS << "get" << TargetName << "SubRegTable(), "
+ << SubRegIndices.size() << ");\n\n";
+ else
+ OS << "NULL, 0);\n\n";
EmitRegMapping(OS, Regs, true);
assert(Regs && "Cannot expand CalleeSavedRegs instance");
// Emit the *_SaveList list of callee-saved registers.
- OS << "static const unsigned " << CSRSet->getName()
+ OS << "static const uint16_t " << CSRSet->getName()
<< "_SaveList[] = { ";
for (unsigned r = 0, re = Regs->size(); r != re; ++r)
OS << getQualifiedName((*Regs)[r]) << ", ";
projects / oota-llvm.git / blobdiff