//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting a description of the target
#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
#include "Record.h"
+#include <algorithm>
+#include <iostream>
using namespace llvm;
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
- EmitSourceFileHeader("Target Instruction Enum Values", OS);
+static void PrintDefList(const std::vector<Record*> &Uses,
+ unsigned Num, std::ostream &OS) {
+ OS << "static const unsigned ImplicitList" << Num << "[] = { ";
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ OS << getQualifiedName(Uses[i]) << ", ";
+ OS << "0 };\n";
+}
- CodeGenTarget Target;
+//===----------------------------------------------------------------------===//
+// Instruction Itinerary Information.
+//===----------------------------------------------------------------------===//
- // We must emit the PHI opcode first...
- Record *InstrInfo = Target.getInstructionSet();
- Record *PHI = InstrInfo->getValueAsDef("PHIInst");
+struct RecordNameComparator {
+ bool operator()(const Record *Rec1, const Record *Rec2) const {
+ return Rec1->getName() < Rec2->getName();
+ }
+};
- std::string Namespace = Target.inst_begin()->second.Namespace;
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector<Record*> DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++)
+ ItinClassMap[DefList[i]->getName()] = i;
+}
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << " enum {\n";
+unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
+ return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
+}
- OS << " " << PHI->getName() << ", \t// 0 (fixed for all targets)\n";
-
- // Print out the rest of the instructions now.
- unsigned i = 0;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II)
- if (II->second.TheDef != PHI)
- OS << " " << II->first << ", \t// " << ++i << "\n";
+//===----------------------------------------------------------------------===//
+// Operand Info Emission.
+//===----------------------------------------------------------------------===//
+
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+ std::vector<std::string> Result;
- OS << " };\n";
- if (!Namespace.empty())
- OS << "}\n";
- EmitSourceFileTail(OS);
+ for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
+ // Handle aggregate operands and normal operands the same way by expanding
+ // either case into a list of operands for this op.
+ std::vector<CodeGenInstruction::OperandInfo> OperandList;
+
+ // This might be a multiple operand thing. Targets like X86 have
+ // registers in their multi-operand operands. It may also be an anonymous
+ // operand, which has a single operand, but no declared class for the
+ // operand.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+
+ if (!MIOI || MIOI->getNumArgs() == 0) {
+ // Single, anonymous, operand.
+ OperandList.push_back(Inst.OperandList[i]);
+ } else {
+ for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
+ OperandList.push_back(Inst.OperandList[i]);
+
+ Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
+ OperandList.back().Rec = OpR;
+ }
+ }
+
+ for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+ Record *OpR = OperandList[j].Rec;
+ std::string Res;
+
+ if (OpR->isSubClassOf("RegisterClass"))
+ Res += getQualifiedName(OpR) + "RegClassID, ";
+ else
+ Res += "0, ";
+ // Fill in applicable flags.
+ Res += "0";
+
+ // Ptr value whose register class is resolved via callback.
+ if (OpR->getName() == "ptr_rc")
+ Res += "|(1<<TOI::LookupPtrRegClass)";
+
+ // Predicate operands. Check to see if the original unexpanded operand
+ // was of type PredicateOperand.
+ if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+ Res += "|(1<<TOI::Predicate)";
+
+ // Optional def operands. Check to see if the original unexpanded operand
+ // was of type OptionalDefOperand.
+ if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
+ Res += "|(1<<TOI::OptionalDef)";
+
+ // Fill in constraint info.
+ Res += ", " + Inst.OperandList[i].Constraints[j];
+ Result.push_back(Res);
+ }
+ }
+
+ return Result;
}
-void InstrInfoEmitter::printDefList(ListInit *LI, const std::string &Name,
- std::ostream &OS) const {
- OS << "static const unsigned " << Name << "[] = { ";
- for (unsigned j = 0, e = LI->getSize(); j != e; ++j)
- if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(j)))
- OS << getQualifiedName(DI->getDef()) << ", ";
- else
- throw "Illegal value in '" + Name + "' list!";
- OS << "0 };\n";
+void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
+ OperandInfoMapTy &OperandInfoIDs) {
+ // ID #0 is for no operand info.
+ unsigned OperandListNum = 0;
+ OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+
+ OS << "\n";
+ const CodeGenTarget &Target = CDP.getTargetInfo();
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+ std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
+ unsigned &N = OperandInfoIDs[OperandInfo];
+ if (N != 0) continue;
+
+ N = ++OperandListNum;
+ OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
+ OS << "};\n";
+ }
}
+//===----------------------------------------------------------------------===//
+// Main Output.
+//===----------------------------------------------------------------------===//
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(std::ostream &OS) {
+ GatherItinClasses();
+
EmitSourceFileHeader("Target Instruction Descriptors", OS);
- CodeGenTarget Target;
+ OS << "namespace llvm {\n\n";
+
+ CodeGenTarget &Target = CDP.getTargetInfo();
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
- Record *PHI = InstrInfo->getValueAsDef("PHIInst");
-
- // Emit empty implicit uses and defs lists
- OS << "static const unsigned EmptyImpUses[] = { 0 };\n"
- << "static const unsigned EmptyImpDefs[] = { 0 };\n";
- // Emit all of the instruction's implicit uses and defs...
+ // Keep track of all of the def lists we have emitted already.
+ std::map<std::vector<Record*>, unsigned> EmittedLists;
+ unsigned ListNumber = 0;
+
+ // Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
Record *Inst = II->second.TheDef;
- ListInit *LI = Inst->getValueAsListInit("Uses");
- if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpUses", OS);
- LI = Inst->getValueAsListInit("Defs");
- if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpDefs", OS);
+ std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
+ if (!Uses.empty()) {
+ unsigned &IL = EmittedLists[Uses];
+ if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
+ }
+ std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
+ if (!Defs.empty()) {
+ unsigned &IL = EmittedLists[Defs];
+ if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
+ }
}
- OS << "\nstatic const TargetInstrDescriptor " << TargetName
+ OperandInfoMapTy OperandInfoIDs;
+
+ // Emit all of the operand info records.
+ EmitOperandInfo(OS, OperandInfoIDs);
+
+ // Emit all of the TargetInstrDesc records in their ENUM ordering.
+ //
+ OS << "\nstatic const TargetInstrDesc " << TargetName
<< "Insts[] = {\n";
- emitRecord(Target.getPHIInstruction(), 0, InstrInfo, OS);
+ std::vector<const CodeGenInstruction*> NumberedInstructions;
+ Target.getInstructionsByEnumValue(NumberedInstructions);
- unsigned i = 0;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II)
- if (II->second.TheDef != PHI)
- emitRecord(II->second, ++i, InstrInfo, OS);
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
+ emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
+ OperandInfoIDs, OS);
OS << "};\n";
- EmitSourceFileTail(OS);
+ OS << "} // End llvm namespace \n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
- Record *InstrInfo, std::ostream &OS) {
- OS << " { \"";
- if (Inst.Name.empty())
- OS << Inst.TheDef->getName();
- else
- OS << Inst.Name;
- OS << "\",\t-1, -1, 0, false, 0, 0, 0, 0";
+ Record *InstrInfo,
+ std::map<std::vector<Record*>, unsigned> &EmittedLists,
+ const OperandInfoMapTy &OpInfo,
+ std::ostream &OS) {
+ int MinOperands = 0;
+ if (!Inst.OperandList.empty())
+ // Each logical operand can be multiple MI operands.
+ MinOperands = Inst.OperandList.back().MIOperandNo +
+ Inst.OperandList.back().MINumOperands;
+
+ OS << " { ";
+ OS << Num << ",\t" << MinOperands << ",\t"
+ << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
+ << ",\t\"" << Inst.TheDef->getName() << "\", 0";
// Emit all of the target indepedent flags...
- if (Inst.isReturn) OS << "|M_RET_FLAG";
- if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
- if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
- if (Inst.isCall) OS << "|M_CALL_FLAG";
- if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
- if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
+ if (Inst.isReturn) OS << "|(1<<TID::Return)";
+ if (Inst.isBranch) OS << "|(1<<TID::Branch)";
+ if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+ if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
+ if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
+ if (Inst.isCall) OS << "|(1<<TID::Call)";
+ if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
+ if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
+ if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
+ if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
+ if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
+ if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
+ if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
+ if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
+ if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
+ if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
+ if (Inst.usesCustomDAGSchedInserter)
+ OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
+ if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
+ if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
+ if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
OS << ", 0";
// Emit all of the target-specific flags...
OS << ", ";
// Emit the implicit uses and defs lists...
- LI = Inst.TheDef->getValueAsListInit("Uses");
- if (!LI->getSize())
- OS << "EmptyImpUses, ";
- else
- OS << Inst.TheDef->getName() << "ImpUses, ";
-
- LI = Inst.TheDef->getValueAsListInit("Defs");
- if (!LI->getSize())
- OS << "EmptyImpDefs ";
- else
- OS << Inst.TheDef->getName() << "ImpDefs ";
+ std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
+ if (UseList.empty())
+ OS << "NULL, ";
+ else
+ OS << "ImplicitList" << EmittedLists[UseList] << ", ";
+
+ std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
+ if (DefList.empty())
+ OS << "NULL, ";
+ else
+ OS << "ImplicitList" << EmittedLists[DefList] << ", ";
+ // Emit the operand info.
+ std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
+ if (OperandInfo.empty())
+ OS << "0";
+ else
+ OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
+
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
+
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
IntInit *ShiftInt, std::ostream &OS) {
if (Val == 0 || ShiftInt == 0)
RecordVal *RV = R->getValue(Val->getValue());
int Shift = ShiftInt->getValue();
- if (RV == 0 || RV->getValue() == 0)
- throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
+ if (RV == 0 || RV->getValue() == 0) {
+ // This isn't an error if this is a builtin instruction.
+ if (R->getName() != "PHI" &&
+ R->getName() != "INLINEASM" &&
+ R->getName() != "DBG_LABEL" &&
+ R->getName() != "EH_LABEL" &&
+ R->getName() != "GC_LABEL" &&
+ R->getName() != "DECLARE" &&
+ R->getName() != "EXTRACT_SUBREG" &&
+ R->getName() != "INSERT_SUBREG" &&
+ R->getName() != "IMPLICIT_DEF" &&
+ R->getName() != "SUBREG_TO_REG")
+ throw R->getName() + " doesn't have a field named '" +
+ Val->getValue() + "'!";
+ return;
+ }
Init *Value = RV->getValue();
if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
Init *I = BI->convertInitializerTo(new IntRecTy());
if (I)
if (IntInit *II = dynamic_cast<IntInit*>(I)) {
- if (II->getValue())
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ if (II->getValue()) {
+ if (Shift)
+ OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ else
+ OS << "|" << II->getValue();
+ }
return;
}
} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
- if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ if (II->getValue()) {
+ if (Shift)
+ OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ else
+ OS << II->getValue();
+ }
return;
}
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